JAJSIR5 データシート

Table 11-23 lists the memory-mapped registers for the SPI. All registers not listed in Table 11-23 should be considered as reserved locations and the register contents should not be modified.

Table 11-23 SPI Registers

Acronym	Register Name	Section
DEV_REV	Device Revision	Go
DEV_ID	Device ID	Go
DEV_STAT1	Device Status 1	Go
DEV_STAT2	Device Status 2	Go
DEV_CFG1	Device Configuration 1	Go
DEV_CFG2	Device Configuration 2	Go
DEV_CFG3	Device Configuration 3	Go
DEV_CFG4	Device Configuration 4	Go
SAFETY_CFG1	Safety Configuration 1	Go
SAFETY_CFG2	Safety Configuration 2	Go
SAFETY_CFG3	Safety Configuration 3	Go
SAFETY_CFG4	Safety Configuration 4	Go
SAFETY_CFG5	Safety Configuration 5	Go
SAFETY_CFG6	Safety Configuration 6	Go
SAFETY_CFG8	Safety Configuration 8	Go
EXT_VMON1_CFG	External VMON1 Configuration	Go
EXT_VMON2_CFG	External VMON2 Configuration	Go
PWR_CTRL	Power Control	Go
CLK_MON_CTRL	Clock Monitor Control	Go
VMON_UV_STAT	VMON Undervoltage Status	Go
VMON_OV_STAT	VMON Overvoltage Status	Go
EXT_VMON_STAT	External VMON Status	Go
SAFETY_BUCK1_STAT1	Safety BUCK1 Status 1	Go
SAFETY_BUCK1_STAT2	Safety BUCK1 Status 2	Go
SAFETY_BUCK2_STAT1	Safety BUCK2 Status 1	Go
SAFETY_BUCK2_STAT2	Safety BUCK2 Status 2	Go
SAFETY_BOOST_STAT1	Safety BOOST Status 1	Go
SAFETY_BOOST_STAT2	Safety BOOST Status 2	Go
SAFETY_ERR_STAT1	Safety Error Status 1	Go
SAFETY_CLK_STAT	Safety Clock Status	Go
SAFETY_CLK_WARN_STAT	Safety Clock Warning Status	Go
SAFETY_ABIST_ERR_STAT1	Safety ABIST Error Status 1	Go
SAFETY_ABIST_ERR_STAT2	Safety ABIST Error Status 2	Go
SAFETY_ABIST_ERR_STAT3	Safety ABIST Error Status 3	Go
SAFETY_ABIST_ERR_STAT4	Safety ABIST Error Status 4	Go
SAFETY_ABIST_ERR_STAT5	Safety ABIST Error Status 5	Go
SAFETY_ABIST_ERR_STAT6	Safety ABIST Error Status 6	Go
SAFETY_LBIST_ERR_STAT	Safety LBIST Error Status	Go
SAFETY_ERR_STAT2	Safety Error Status 2	Go
SAFETY_ERR_STAT3	Safety Error Status 3	Go
SAFETY_ERR_STAT4	Safety Error Status 4	Go
SPI_TRANSFER_STAT	SPI Transfer Status	Go
SAFETY_ABIST_CTRL	Safety ABIST Control	Go
SAFETY_LBIST_CTRL	Safety LBIST Control	Go
SAFETY_CHECK_CTRL	Safety Check Control	Go
SAFETY_ERR_PWM_HMAX_CFG	Safety Error PWM HMAX Configuration	Go
SAFETY_ERR_PWM_HMIN_CFG	Safety Error PWM HMIN Configuration	Go
SAFETY_ERR_PWM_LMAX_CFG	Safety Error PWM LMAX Configuration	Go
SAFETY_ERR_PWM_LMIN_CFG	Safety Error PWM LMIN Configuration	Go
SAFETY_PWD_TH_CFG	Safety PWD Threshold Configuration	Go
SAFETY_DEV_CFG_CRC	Safety Device Configuration CRC	Go
DIAG_CTRL	Diagnostic Mux Control	Go
DIAG_MUX_SEL	Diagnostic Mux Select	Go
WDT_WIN1_CFG	Watchdog Window 1 Configuration	Go
WDT_WIN2_CFG	Watchdog Window 2 Configuration	Go
WDT_Q&A_CFG	Watchdog Q&A Configuration	Go
WDT_QUESTION_VALUE	Watchdog Question Value	Go
WDT_STATUS	Watchdog Status	Go
WDT_ANSWER	Watchdog Answer	Go
OFF_STATE_L_STAT	OFF State L Status	Go

Complex bit access types are encoded to fit into small table cells. Table 11-24 shows the codes that are used for access types in this section.

Table 11-24 SPI Register Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value.
-X		Value depends on the orderable part number or as described.

DEV_REV Register

DEV_REV is shown in Figure 11-38 and described in Table 11-25.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read-Only (RD_DEV_REV)

Figure 11-38 Device Revision (DEV_REV) Register

7	6	5	4	3	2	1	0
MAJOR_REV[3:0]				MINOR_REV[3:0]
R-0010b				R-0000b

Table 11-25 DEV_REV Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	MAJOR_REV[3:0]	R	0010b	Device major revision.
3-0	MINOR_REV[3:0]	R	0001b	Device minor revision.

DEV_ID Register

DEV_ID is shown in Figure 11-39 and described in Table 11-26. For DEV_ID register bits initial values refer to device Technical Reference Manual (TRM).

Return to Table 11-23

Initialization source: NPOR
Controller access: Read-Only (RD_DEV_ID1)
No dedicated EEPROM bits are required.

Figure 11-39 Device ID (DEV_ID) Register

7

6

5

4

3

2

1

0

Table 11-26 DEV_ID Register Field Descriptions

Bit	Field	Type	Initial State	Description
4	NRES_EXT_DELAY	R	0b	NRES Extension Delay configuration 0b = LONG NRES Extension Delay (32 ms - 33 ms). 1b = SHORT NRES Extension Delay (2 ms - 3 ms)
3	RESERVED	R	0b	Reserved.

Bit

Field

Type

Initial State

Description

4

NRES_EXT_DELAY

R

0b

NRES Extension Delay configuration

0b = LONG NRES Extension Delay (32 ms - 33 ms).

1b = SHORT NRES Extension Delay (2 ms - 3 ms)

3

RESERVED

R

0b

Reserved.

DEV_STAT1 Register

DEV_STAT1 is shown in Figure 11-40 and described in Table 11-27.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read-Only (RD_DEV_STAT1)

Figure 11-40 Device Status 1 (DEV_STAT1) Register

7	6	5	4	3	2	1	0
FSM[2:0]			RESERVED	AUTO_START_DIS	CFG_LOCK	CTRL_BIST_LOCK	CTRL_LOCK
R-000b			R-0b	R-0b	R-1b	R-1b	R-1b

Table 11-27 DEV_STAT1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-5	FSM[2:0]	R	000b	Current device state. In the RESET state, the devices SPI communication is disabled and the device returns all 0 s to any SPI command. In the OFF state, the device is fully powered down including the digital core. 000b = Not used. 001b = DIAGNOSTIC state. 010b = ACTIVE state. 100b = SAFE state.
4	RESERVED	R	0b	Reserved
3	AUTO_START_DIS	R	0b	Auto restart enable-latch value which controls whether device automatic restart is allowed when the device goes to the OFF state while the WAKE input is high. This bit is set by the SET_AUTO_START_DIS command with data 0xAA and cleared by the CLR_AUTO_START_DIS command with data 0x55. NOTE: This bit is NOT initialized by an NPOR event unless the event is preceded by loss of battery supply at the VIN, VINA, and VIN_SAFE pins. This bit is set to 1b every time a valid VREG OV event is detected. 0b = Auto restart is enabled when the device reaches the OFF state and the WAKE input is still high. 1b = Auto restart is disabled when the device goes to the OFF state and the WAKE input is still high. To start up the device, the WAKE input must toggle from low to high.
2	CFG_LOCK	R	1b	Write-protect flag for the device configuration registers. This bit is set by the SET_CFG_LOCK SPI command with data 0x55 while the device is in the DIAGNOSTIC, or when the device exits the DIAGNOSTIC state, or on completion of the LBIST run. This bit is cleared by the CLR_CFG_LOCK SPI command with data 0xAA while the device is in the DIAGNOSTIC state.
1	CTRL_BIST_LOCK	R	1b	Write-protect flag for the SAFETY_ABIST_CTRL and SAFETY_LBIST_CTRL registers. This bit is set by the SET_CTRL_LOCK SPI command with data 0x55 while the device is in the DIAGNOSTIC, ACTIVE or SAFE state, or when the device exits the DIAGNOSTIC, ACTIVE or SAFE state, or on completion of the LBIST run. This bit is cleared by the CLR_CTRL_LOCK SPI command with data 0xAA while the device is in the DIAGNOSTIC, ACTIVE or SAFE state.
0	CTRL_LOCK	R	1b	Write-protect flag for device control registers. This bit is set by the SET_CTRL_LOCK SPI command with data 0x55 while the device is in the DIAGNOSTIC, ACTIVE, or SAFE state, or when the device exits the DIAGNOSTIC state, or on completion of the LBIST run. This bit is cleared by the CLR_CTRL_LOCK SPI command with data 0xAA while the device is in the DIAGNOSTIC, ACTIVE, or SAFE state.

DEV_STAT2 Register

DEV_STAT2 is shown in Figure 11-41 and described in Table 11-28.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_DEV_STAT2)

Figure 11-41 Device Status 2 (DEV_STAT2) Register

7	6	5	4	3	2	1	0
RESERVED	DIAG_EXIT_MASK	SAFE_TO_DIS	MCU_RST_REQ_FLAG	SYNC_IN	MCU_ERR_IN	WAKE_L	WAKE
R-0b	R-0b	R-1b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 11-28 DEV_STAT2 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	DIAG_EXIT_MASK	R	0b	Status of the exit-mask bit for the DIAGNOSTIC state. This bit is set by the MASK_DIAG_EXIT command with 0x55h data and cleared by the UNMASK_DIAG_EXIT command with 0xAA data. 0b = The device transitions to the SAFE state from the DIAGNOSTIC state when the DIAGNOSITC state time-out timer expires. 1b = The device does not transition to the SAFE state from the DIAGNOSTIC state as the DIAGNOSITC state time-out timer is kept in reset.
5	SAFE_TO_DIS	R	1b	Status of the SAFE state time-out function. This bit is set by the DIS_SAFE_TO SPI command with data 0x55 and only when the device is in the DIAGNOSTIC state, and is cleared by the EN_SAFE_TO SPI command with data 0xAA only when the device is in the DIAGNOSTIC state. 0b = The device transitions to the RESET state from the SAFE state when the SAFE state time-out timer (SAFE_TO[1:0]) expires. 1b = The device does not transition to the RESET state from the SAFE state unless following event occurs: — Global RESET condition. — Global OFF state condition. — MCU SW RESET request (through the NCU_RST_RQ SPI command with data 0x5A). — MCU request transition to the DIAGNOSTIC state (SAFE_EXIT command).
4	MCU_RST_REQ_FLAG	R	0b	Flag indicating that the last transition to the RESET state was caused by the MCU through the MCU_RST_REQ SPI command with data 0x5A. The MCU_RST_REQ command can be issued while the device is in the DIAGNOSTIC, ACTIVE, or SAFE state. This bit is not cleared by read command. 0b = No reset requested by the MCU. 1b = Reset requested by the MCU.
3	SYNC_IN	R	0b	Detection of an external clock at the SYNC_IN pin. This bit is valid only when the SMPS_CLK_SRC bit in the DEV_ID register is set to 1b. This bit is set when the SYNC_IN clock monitor detects that clock is driven to SYNC_IN input pin. When the SYNC_IN clock monitor is disabled, this bit is set to 0b. When the SYNC_IN clock monitor is enabled, this bit is set to 1b (when the clock at the SYNC_IN pin is in range) or 0 (when the clock at the SYNC_IN pin is not in range). 0b = No valid clock is detected at the SYNC_IN pin, or DIG_CLK_MON1 is not enabled. 1b = Valid clock detected at the SYNC_IN pin while DIG_CLK_MON1 is enabled.
2	MCU_ERR_IN	R	0b	The MCU_ERR pin state. 0b = MCU_ERR input pin is in low state. 1b = MCU_ERR input pin is in high state.
1	WAKE_L	R	0b	Wake-up event detection (latched and deglitched). 0b =No rising-edge event detected at WAKE pin, or previous rising-edge event on the WAKE pin is cleared by the CLR_WAKE_LATCH command with data 0x8E or failure conditions that force the device transition to the OFF state (or anytime the device transitions to the OFF state). 1b = Rising-edge event detected at WAKE pin.
0	WAKE	R	0b	The WAKE pin state (deglitched). 0b = The WAKE pin is in low state. 1b = The WAKE pin is in high state.

DEV_CFG1 Register

DEV_CFG1 is shown in Figure 11-42 and described in Table 11-29.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_DEV_CFG1)
Write (WR_DEV_CFG1). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the device-configuration CRC (DEV_CFG_CRC).

Figure 11-42 Device Configuration 1 (DEV_CFG1) Register

7	6	5	4	3	2	1	0
BOOST_OV_RST_EN	RESERVED	BUCK2_OV_RST_EN	BUCK1_OV_RST_EN	BOOST_UV_RST_EN	RESERVED	BUCK2_UV_RST_EN	BUCK1_UV_RST_EN
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-1b	R/W-0b	R/W-1b	R/W-1b

Table 11-29 DEV_CFG1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	BOOST_OV_RST_EN	R/W	0b	Configuration of BOOST OV event for a global RESET event. 0b = BOOST OV is not a global RESET event. 1b = BOOST OV is a global RESET event.
6	RESERVED	R/W	0b	Reserved
5	BUCK2_OV_RST_EN	R/W	0b	Configuration of BUCK2 OV event for a global RESET event. 0b = BUCK2 OV is not a global RESET event. 1b = BUCK2 OV is a global RESET event.
4	BUCK1_OV_RST_EN	R/W	0b	Configuration of BUCK1 OV event for a global RESET event. 0b = BUCK1 OV is not a global RESET event. 1b = BUCK1 OV is a global RESET event.
3	BOOST_UV_RST_EN	R/W	1b	Configuration of BOOST UV event for a global RESET event. 0b = BOOST UV is not a global RESET event. 1b = BOOST UV is a global RESET event.
2	RESERVED	R/W	0b	Reserved
1	BUCK2_UV_RST_EN	R/W	1b	Configuration of BUCK2 UV event for a global RESET event. 0b = BUCK2 UV is not a global RESET event. 1b = BUCK2 UV is a global RESET event.
0	BUCK1_UV_RST_EN	R/W	1b	Configuration of BUCK1 UV event for a global RESET event. 0b = BUCK1 UV is not a global RESET event. 1b = BUCK1 UV is a global RESET event.

DEV_CFG2 Register

DEV_CFG2 is shown in Figure 11-43 and described in Table 11-30.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_DEV_CFG2)
Write (WR_DEV_CFG2). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.
Note: Anytime a x_IRQ_EN bit is set to 1b and the respective analog condition occurs, the activated ENDRV/nIRQ driver is disabled (drives the activated ENDRV/nIRQ pin low), the ENDRV_EN control bit is cleared, and the device transitions to the SAFE state.

Figure 11-43 Device Configuration 2 (DEV_CFG2) Register

7	6	5	4	3	2	1	0
RESERVED				BOOST_OT_WARN_IRQ_EN	RESERVED	BUCK2_OT_WARN_IRQ_EN	BUCK1_OT_WARN_IRQ_EN
R-0000b				R/W-0b	R-0b	R/W-0b	R/W-0b

Table 11-30 DEV_CFG2 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	RESERVED	R/W	0000b	Reserved.
3	BOOST_OT_WARN_IRQ_EN	R/W	0b	Configuration of BOOST OT warning event for a global nIRQ event. 0b = BOOST OT WARN is not a global nIRQ event. The BOOST_OT_WARN status bit is set. 1b = BOOST OT WARN is a global nIRQ event. The BOOST_OT_WARN status bit is set. The device pulls the ENDRV/nIRQ pin low and clears the ENDRV_EN control bit.
2	RESERVED	R/W	0b	Reserved
1	BUCK2_OT_WARN_IRQ_EN	R/W	0b	Configuration of BUCK2 OT warning event for a global nIRQ event. 0b = BUCK2 OT WARN is not a global nIRQ event. The BUCK2_OT_WARN status bit is set. 1b = BUCK2 OT WARN is a global nIRQ event. The BUCK2_OT_WARN status bit is set. The device pulls the ENDRV/nIRQ pin low and clears the ENDRV_EN control bit.
0	BUCK1_OT_WARN_IRQ_EN	R/W	0b	Configuration of BUCK1 OT warning event for a global nIRQ event. 0b = BUCK1 OT WARN is not a global nIRQ event. The BUCK1_OT_WARN status bit is set. 1b = BUCK1 OT WARN is a global nIRQ event. The BUCK1_OT_WARN status bit is set. The device pulls the ENDRV/nIRQ pin low and clears the ENDRV_EN control bit.

DEV_CFG3 Register

DEV_CFG3 is shown in Figure 11-44 and described in Table 11-31.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_DEV_CFG3)
Write (WR_DEV_CFG3). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-44 Device Configuration 3 (DEV_CFG3) Register

7	6	5	4	3	2	1	0
RESERVED			VIN_BAD_IRQ_EN	RESERVED
R-000b			R/W-0b	R-0000b

Table 11-31 DEV_CFG3 Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-5

RESERVED

R

000b

Reserved.

4

VIN_BAD_IRQ_EN

R/W

0b

Configuration of VIN BAD event for a global nIRQ event.

0b = VIN BAD is not a global nIRQ event.

1b = VIN BAD is a global nIRQ event. The device pulls the ENDRV/nIRQ pin low and clears the ENDRV_EN control bit.

3-0

RESERVED

R

0000b

Reserved.

DEV_CFG4 Register

DEV_CFG4 is shown in Figure 11-45 and described in Table 11-32.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_DEV_CFG4)
Write (WR_DEV_CFG4). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-45 Device Configuration 4 (DEV_CFG4) Register

7	6	5	4	3	2	1	0
RESERVED		VIN_BAD_TH[1:0]		RESERVED		NRST_EXT
R-00b		R/W-00b		R-00b		R/W-11

Table 11-32 DEV_CFG4 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved
5-4	VIN_BAD_TH[1:0]	R	00b	VIN BAD detection threshold level. 00b = 6.2 V 01b = 7.2 V 00b = 8.2 V 11b = 8.2 V
3-2	RESERVED	R	00b	Reserved
1-0	NRES_EXT	R	11b	MCU RESET extension delay (t_{NRES_EXT}). The extension delay range ordering is controlled by EEPROM bit NRES_EXT_DELAY latched as DEV_ID register bit #4. When EEPROM mapped configuration NRES_EXT_DELAY bit is 0b: 00b = 2 ms to 3 ms 01b = 11 ms to 12 ms 10b = 21 ms to 22 ms 11b = 31 ms to 32 ms When EEPROM mapped configuration NRES_EXT_DELAY bit is 1b: 00b = 31 ms to 32 ms 01b = 21 ms to 22 ms 10b = 11 ms to 12 ms 11b = 2 ms to 3 ms

SAFETY_CFG1 Register

SAFETY_CFG1 is shown in Figure 11-46 and described in Table 11-33.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_CFG1)
Write (WR_SAFETY_CFG1). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-46 Safety Configuration 1 (SAFETY_CFG1) Register

7	6	5	4	3	2	1	0
RESERVED		SAFE_TO[1:0]		SAFE_LOCK_TH[3:0]
R-00b		R-00b		R-0000b

Table 11-33 SAFETY_CFG1 Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-6

RESERVED

R

00b

Reserved

5-4

SAFE_TO[1:0]

R

00b

The SAFE state time-out

00b = 640 ms

01b = 320 ms

00b = 5 ms

00b = 1.25 ms

3-0

SAFE_LOCK_TH[3:0]

R

0000b

The SAFE state lock threshold.
These bits set the corresponding DEV_ERR_CNT[3:0] threshold at which the device remains in the SAFE state depending on the SAFE_TO_DIS bit setting (bit 5 in the SAFETY_STAT2 register).
— When the SAFE_TO_DIS bit is set to 0b, regardless of the SAFE_LOCK_TH[3:0] bit settings, the device transitions to the RESET state from the SAFE state when the SAFE state time-out timer expires.
— When the SAFE_TO_DIS bit is set to 1b:
— If DEV_ERR_CNT[3:0] ≤ SAFE_LOCK_TH[3:0], the device transitions to the RESET state from the SAFE state when the SAFE state time-out timer expires.
— If DEV_ERR_CNT[3:0] > SAFE_LOCK_TH[3:0], the device remains locked in the SAFE state.

SAFETY_CFG2 Register

SAFETY_CFG2 is shown in Figure 11-47 and described in Table 11-34.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_CFG2)
Write (WR_SAFETY_CFG2). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-47 Safety Configuration 2 (SAFETY_CFG2) Register

7	6	5	4	3	2	1	0
CLK_WARN_RESP_EN	RESERVED	ABIST_SCHED_EN	AUTO_BIST_DIS	ABIST_ACTIVE_FAIL_RESP	ENDRV_ERR_RESP_EN	NRES_ERR_RST_EN	NRES_ERR_SAFE_EN
R/W-0b	R-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 11-34 SAFETY_CFG2 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	CLK_WARN_RESP_EN	R/W	0b	Enables and disables the device transition from the DIAGNOSTIC or ACTIVE state to the SAFE state when any digital clock monitor detects accuracy warning listed in the SAFETY_CLK_WARN_STAT register. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
6	RESERVED	R	0b	Reserved
5	ABIST_SCHED_EN	R/W	0b	Enables and disables the ABIST scheduler in the ACTIVE state. 0b = ABIST scheduler is disabled in the ACTIVE state. 1b = ABIST scheduler is enabled when the device is in the ACTIVE state and if any of ABIST_GROUPx_START control bits in the SAFETY_ABIST_CTRL register is set.
4	AUTO_BIST_DIS	R/W	0b	Enables and disables automatic ABIST and LBIST run during NRES extension when the device enters the RESET state from one of the other operating states (DIAGNOSTIC, ACTIVE, or SAFE state). 0b = Automatic ABIST and LBIST enabled. 1b = Automatic ABIST and LBIST disabled.
3	ABIST_ACTIVE_FAIL_RESP	R/W	0b	Enables and disables the device transition to the SAFE state from the DIAGNOSTIC or ACTIVE state when any of the ABIST fails. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
2	ENDRV_ERR_RESP_EN	R/W	0b	Enables and disables the device transition to the SAFE state from the DIAGNOSTIC or ACTIVE state when the ENDRV/nIRQ driver error is detected. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
1	NRES_ERR_RST_EN	R/W	0b	Enables and disables the device transition to the RESET state from the DIAGNOSTIC, ACTIVE, or SAFE state when the NRES driver error is detected. NOTE: If both the NRES_ERR_RST_EN and NRES_ERR_SAFE_EN bits are set, the NRES_ERR_RST_EN has priority. 0b = Transition to the RESET state disabled. 1b = Transition to the RESET state enabled.
0	NRES_ERR_SAFE_EN	R/W	0b	Enables and disables the device transition to the SAFE state from the DIAGNOSTIC or ACTIVE state when the NRES driver error is detected. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.

SAFETY_CFG3 Register

SAFETY_CFG3 is shown in Figure 11-48 and described in Table 11-35.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_CFG3)
Write (WR_SAFETY_CFG3). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-48 Safety Configuration 3 (SAFETY_CFG3) Register

7	6	5	4	3	2	1	0
RESERVED	SSM_EN	RESERVED	SPI_CRC_CFG	WD_CFG	MCU_ESM_CFG	WD_RST_EN	MCU_ESM_RST_EN
R-0b	R/W-0b	R-0b	R/W-0b	R/W-0b	R/W-0b	R/W-1b	R/W-0b

Table 11-35 SAFETY_CFG3 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	SSM_EN	R/W	0b	Enables and disables internal Adaptively Randomized Spread Spectrum (ARSS) modulation. 0b = Internal ARSS modulation is disabled. 1b = Internal ARSS modulation is enabled.
5	RESERVED	R	0b	Reserved.
4	SPI_CRC_CFG	R/W	0b	Enables and disables CRC protection on SPI communication. 0b = SPI Frame CRC protection disabled. 1b = SPI Frame CRC protection enabled.
3	WD_CFG	R/W	0b	Watchdog mode configuration. NOTE: This bit is initialized when the device enters the RESET state. 0b = Q&A Configuration with total of 4 watchdog answers during watchdog cycle. 1b = Q&A Configuration with only single watchdog answer during the OPEN window.
2	MCU_ESM_CFG	R/W	0b	MCU Error signal monitor configuration. NOTE: This bit is initialized when the device enters the RESET state. 0b = MCU ERORR pin low condition monitor (TMS570 mode). 1b = PWM mode.
1	WD_RST_EN	R/W	1b	Enables the device transition either to the RESET state or to the SAFE state from the DIAGNOSTIC or ACTIVE state when WD_FAIL_CNT reaches WD_FC_RST_TH. NOTE: This bit is initialized when the device enters the RESET state. The bit is 'masked (but not cleared) when the device enters the SAFE state to prevent the device transition to the RESET state. 0b = The device transitions to the SAFE state. 1b = The device transitions to the RESET state.
0	MCU_ESM_RST_EN	R/W	0b	Enables the device transition either to the RESET state or to the SAFE state from the DIAGNOSTIC or ACTIVE state when MCU_ESM_FC reaches MCU_ESM_FC_RST_TH. NOTE: This bit is initialized when the device enters the RESET state. 0b = The device transitions to the SAFE state. 1b = The device transitions to the RESET state.

SAFETY_CFG4 Register

SAFETY_CFG4 is shown in Figure 11-49 and described in Table 11-36.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_SAFETY_CFG4)
Write (WR_SAFETY_CFG4). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-49 Safety Configuration 4 (SAFETY_CFG4) Register

7	6	5	4	3	2	1	0
MCU_ESM_FC_RST_TH				MCU_ESM_FC_ENDRV_TH
R/W-1111b				R/W-1000b

Table 11-36 SAFETY_CFG4 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	MCU_ESM_FC_RST_TH	R/W	1111b	MCU_ESM_FC threshold at which the device transition to the RESET state when device is in the ACTIVE, DIAGNOSTIC, or SAFE state, if MCU_ESM_RST_EN = 1b. If MCU_ESM_RST_EN = 0b the device transition to the SAFE state at this threshold.
3-0	MCU_ESM_FC_ENDRV_TH	R/W	1000b	MCU_ESM_FC threshold at which the device transition to the SAFE state when device is in the ACTIVE state.

SAFETY_CFG5 Register

SAFETY_CFG5 is shown in Figure 11-50 and described in Table 11-37.

Return to Table 11-23

Initialization source: NPOR, RESET, WD_CFG change
Controller access: Read (RD_SAFETY_CFG5)
Write (WR_SAFETY_CFG5). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-50 Safety Configuration 5 (SAFETY_CFG5) Register

7	6	5	4	3	2	1	0
WD_FC_RST_TH				WD_FC_ENDRV_TH
R/W-1111b				R/W-0101b

Table 11-37 SAFETY_CFG5 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	WD_FC_RST_TH	R/W	1111b	WD_FAIL_CNT threshold at which the device sets the WD_RST_FAIL status bit and transitions either to the RESET state (when WD_RST_EN = 1b) or to the SAFE state (when WD_RST_EN = 0b).
3-0	WD_FC_ENDRV_TH	R/W	0101b	WD_FAIL_CNT threshold at which device sets the WD_ENDRV_FAIL status bit and drives the ENDRV/nIRQ output low. NOTE: No state transition to the SAFE state will occur.

SAFETY_CFG6 Register

SAFETY_CFG6 is shown in Figure 11-51 and described in Table 11-38.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_CFG6)
Write (WR_SAFETY_CFG6). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-51 Safety Configuration 6 (SAFETY_CFG6) Register

7	6	5	4	3	2	1	0
RESERVED		BUCK1_SCG_OFF_EN	BUCK1_OVP_OFF_EN	BUCK1_LS_SINK_OVC_OFF_EN	RESERVED	BUCK1_PGND_LOSS_OFF_EN	BUCK1_OT_OFF_EN
R-00b		R/W-1b	R/W-1b	R/W-1b	R-0b	R/W-1b	R/W-1b

Table 11-38 SAFETY_CFG6 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved.
5	BUCK1_SCG_OFF_EN	R/W	1b	Enables device transition either to the OFF state or to the SAFE state when the BUCK1 short-circuit-to-ground event is detected. 0b = The device transitions to the SAFE state. 1b = The device transitions to the OFF state.
4	BUCK1_OVP_OFF_EN	R/W	1b	Enables device transition either to the OFF state or to the SAFE state when the BUCK1 overvoltage protection event is detected. 0b = The device transitions to the SAFE state. 1b = The device transitions to the OFF state.
3	BUCK1_LS_SINK_OVC_OFF_EN	R/W	1b	Enables device transition either to the OFF state or to the SAFE state when the BUCK1 LS sink overcurrent event is detected 0b = The device transitions to the SAFE state. 1b = The device transitions to the OFF state.
2	RESERVED	R	0b	Reserved.
1	BUCK1_PGND_LOSS_OFF_EN	R/W	1b	Enables device transition either to the OFF state or to the SAFE state when the BUCK1 loss-of-ground event is detected. 0b = The device transitions to the SAFE state. 1b = The device transitions to the OFF state.
0	BUCK1_OT_OFF_EN	R/W	1b	Enables device transition either to the OFF state or to the SAFE state when the BUCK1 die overtemperature event is detected. 0b = The device transitions to the SAFE state. 1b = The device transitions to the OFF state.

SAFETY_CFG8 Register

SAFETY_CFG8 is shown in Figure 11-52 and described in Table 11-39.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_CFG8)
Write (WR_SAFETY_CFG8). Write access only in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-52 Safety Configuration 8 (SAFETY_CFG8) Register

7	6	5	4	3	2	1	0
ABIST_SCHED_DLY
R/W-0001 0000b

Table 11-39 SAFETY_CFG8 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	ABIST_SCHED_DLY	R/W	0001 0000b	Programmable time interval between any two scheduled ABIST group of tests. Time interval, t₂, is multiple of programmed watchdog cycles per formula below: t₂ = (ABIST_SCHED_DLY + 1) × 256 × (t_{WD_WIN1} + t_{WD_WIN2}). The time delay between any two scheduled ABIST group of tests can be set in the range from 281.6 ms to 10380.9 s.

EXT_VMON1_CFG Register

EXT_VMON1_CFG is shown in Figure 11-53 and described in Table 11-40.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_EXT_VMON1_CFG)
Write (WR_EXT_VMON1_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. - Protected by the DEV_CFG_CRC.

Figure 11-53 External VMON1 Configuration (EXT_VMON1_CFG) Register

7	6	5	4	3	2	1	0
RESERVED				EXT_VMON1_OV_IRQ_EN	EXT_VMON1_UV_IRQ_EN	EXT_VMON1_UV_RST_EN	EXT_VMON1_OV_RST_EN
R-0000b				R/W-0b	R/W-0b	R/W-Xb	R/W-0b

Table 11-40 EXT_VMON1_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	RESERVED	R	0000b	Reserved
3	EXT_VMON1_OV_IRQ_EN	R/W	0b	Enables and disables device transition to the SAFE state when overvoltage event at EXT_VSENSE1 pin is detected. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
2	EXT_VMON1_UV_IRQ_EN	R/W	0b	Enables and disables device transition to the SAFE state when undervoltage event at EXT_VSENSE1 pin is detected. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
1	EXT_VMON1_UV_RST_EN	R/W	Xb	Enables and disables device transition to the RESET state when undervoltage event at EXT_VSENSE1 pin is detected. NOTE: If both the EXT_VMON1_UV_IRQ_EN and EXT_VMON1_UV_RST_EN bits are set, the EXT_VMON1_UV_RST_EN has priority. 0b = Transition to the RESET state disabled. 1b = Transition to the RESET state enabled. Default state of this bit controlled by EEPROM bit.
0	EXT_VMON1_OV_RST_EN	R/W	0b	Enables and disables device transition to the RESET state when overvoltage event at EXT_VSENSE1 pin is detected. NOTE: If both the EXT_VMON1_OV_IRQ_EN and EXT_VMON1_OV_RST_EN bits are set, the EXT_VMON1_OV_RST_EN has priority. 0b = Transition to the RESET state disabled. 1b = Transition to the RESET state enabled.

EXT_VMON2_CFG Register

EXT_VMON2_CFG is shown in Figure 11-54 and described in Table 11-41.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_EXT_VMON2_CFG)
Write (WR_EXT_VMO2_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-54 External VMON2 Configuration (EXT_VMON2_CFG) Register

7	6	5	4	3	2	1	0
RESERVED				EXT_VMON2_OV_IRQ_EN	EXT_VMON2_UV_IRQ_EN	EXT_VMON2_UV_RST_EN	EXT_VMON2_OV_RST_EN
R-0000b				R/W-0b	R/W-0b	R/W-Xb	R/W-0b

Table 11-41 EXT_VMON2_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	RESERVED	R	000b	Reserved
3	EXT_VMON2_OV_IRQ_EN	R/W	0b	Enables and disables device transition to the SAFE state when overvoltage event at EXT_VSENSE2 pin is detected. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
2	EXT_VMON2_UV_IRQ_EN	R/W	0b	Enables and disables device transition to the SAFE state when undervoltage event at EXT_VSENSE2 pin is detected. 0b = Transition to the SAFE state disabled. 1b = Transition to the SAFE state enabled.
1	EXT_VMON2_UV_RST_EN	R/W	Xb	Enables and disables device transition to the RESET state when undervoltage event at EXT_VSENSE2 pin is detected. NOTE: If both the EXT_VMON2_UV_IRQ_EN and EXT_VMON2_UV_RST_EN bits are set, the EXT_VMON2_UV_RST_EN has priority. 0b = Transition to the RESET state disabled. 1b = Transition to the RESET state enabled. Default state of this bit controlled by EEPROM bit.
0	EXT_VMON2_OV_RST_EN	R/W	0b	Enables and disables device transition to the RESET state when overvoltage event at EXT_VSENSE1 pin is detected. NOTE: If both the EXT_VMON2_OV_IRQ_EN and EXT_VMON2OV_RST_EN bits are set, the EXT_VMON2_OV_RST_EN has priority. 0b = Transition to the RESET state disabled. 1b = Transition to the RESET state enabled.

PWR_CTRL Register

PWR_CTRL is shown in Figure 11-55 and described in Table 11-42.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_PWR_CTRL)
Write (WR_PWR_CTRL). Write access is only available when the CTRL_LOCK bit is set to 0b (DEV_STAT1.CTRL_LOCK bit).
NOTE:

The BUCK1 is always enabled by default, and cannot be disabled through SPI mapped register. The enable or disable of the BUCK1 is controlled through WAKE input and WAKE_L latch under normal operating conditions.
The BUCK1 can be disabled by the internal monitoring and protection circuit, and enabled again after its re-start conditions are met.

Figure 11-55 Power Control (PWR_CTRL) Register

7	6	5	4	3	2	1	0
RESERVED		EXT_VMON2_EN	EXT_VMON1_EN	BOOST_EN	RESERVED	BUCK2_EN	RESERVED
R-00b		R/W-Xb	R/W-Xb	R/W-1b	R-0b	R/W-1b	R-0b

Table 11-42 PWR_CTRL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved.
5	EXT_VMON2_EN	R/W-X	Xb	Enables and disables the external supply monitor at the EXT_VSENSE2 pin. This bit is NOT initialized when the device enters the RESET state. 0b = EXT VMON2 disabled. 1b = EXT VMON2 enabled.
4	EXT_VMON1_EN	R/W-X	Xb	Enables and disables the external supply monitor at the EXT_VSENSE1 pin. This bit is NOT initialized when the device enters the RESET state. 0b = EXT VMON1 disabled. 1b = EXT VMON1 enabled.
3	BOOST_EN	R/W	1b	Enables and disables the BOOST converter. This bit is also cleared to 0b when the BOOST is disabled due to a relevant fault event and when the device transitions to the SAFE state. 0b = The BOOST disabled. 1b = The BOOST enabled.
2	RESERVED	R/W	0b	Reserved
1	BUCK2_EN	R/W	1b	Enables and disables the BUCK2 regulator. This bit is also cleared to 0b when the BUCK2 is disabled due to a relevant fault event and when the device transitions to the SAFE state. 0b = The BUCK2 disabled. 1b = The BUCK2 enabled.
0	RESERVED	R/W	0b	Reserved.

CLK_MON_CTRL Register

CLK_MON_CTRL is shown in Figure 11-56 and described in Table 11-43.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_CLK_MON_CTRL)
Write (WR_CLK_MON_CTRL). Write access is only available when the CTRL_LOCK is set to 0b.

Figure 11-56 Clock Monitor Control Register (CLK_MON_CTRL) Register

7	6	5	4	3	2	1	0
RESERVED	DIG_CLK_MON5_EN	RESERVED	DIG_CLK_MON4_EN	DIG_CLK_MON3_EN	DIG_CLK_MON6_EN	DIG_CLK_MON1_EN	RESERVED
R-0b	R/W-1b	R-0b	R/W-1b	R/W-1b	R/W-1b	R/W-0b	R-0b

Table 11-43 CLK_MON_CTRL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	DIG_CLK_MON5_EN		1b	Enables and disables the DIG_CLK_MON5 for the BOOST converter switching clock. 0b = Clock monitor is disabled. 1b = Clock monitor is enabled.
5	RESERVED	R	0b	Reserved.
4	DIG_CLK_MON4_EN	R/W	1b	Enables and disables the DIG_CLK_MON4 for the BUCK2 regulator switching clock. 0b = Clock monitor is disabled. 1b = Clock monitor is enabled.
3	DIG_CLK_MON3_EN	R/W	1b	Enables and disables the DIG_CLK_MON3 for the BUCK1 regulator switching clock. 0b = Clock monitor is disabled. 1b = Clock monitor is enabled.
2	DIG_CLK_MON6_EN	R/W	1b	Enables and disables the DIG_CLK_MON6 for clock source (PLL or MODCLK) for the switching regulators. 0b = Clock monitor is disabled. 1b = Clock monitor is enabled.
1	DIG_CLK_MON1_EN	R/W	0b	Enables and disables the DIG_CLK_MON1 for external clock at the SYNC_IN pin for synchronization. 0b = Clock monitor is disabled. 1b = Clock monitor is enabled.
0	RESERVED	R	0b	Reserved.

VMON_UV_STAT Register

VMON_UV_STAT is shown in Figure 11-57 and described in Table 11-44.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_VMON_UV_STAT)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-57 VMON Undervoltage Status (VMON_UV_STAT) Register

7	6	5	4	3	2	1	0
RESERVED	VIN_BAD	RESERVED	VREG_UV	BOOST_UV	RESERVED	BUCK2_UV	BUCK1_UV
R-0b	RC-0b	R-0b	RC-0b	RC-0b	R-0b	RC-0b	RC-0b

Table 11-44 VMON_UV_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	VIN_BAD	RC	0b	VIN undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.
5	RESERVED	R	0b	Reserved.
4	VREG_UV	RC	0b	VREG undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.
3	BOOST_UV	RC	0b	BOOST undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.
2	RESERVED	R	0b	Reserved.
1	BUCK2_UV	RC	0b	BUCK2 undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.
0	BUCK1_UV	RC	0b	BUCK1 undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.

VMON_OV_STAT Register

VMON_OV_STAT is shown in Figure 11-58 and described in Table 11-45.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_VMON_OV_STAT)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-58 VMON Overvoltage Status (VMON_OV_STAT) Register

7	6	5	4	3	2	1	0
VIO_OV	VIN_OV	RESERVED	VREG_OV	BOOST_OV	RESERVED	BUCK2_OV	BUCK1_OV
RC-0b	RC-0b	R-0b	RC-0b	RC-0b	R-0b	RC-0b	RC-0b

Table 11-45 VMON_OV_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	VIO_OV	RC	0b	VIO overvoltage error flag. 0b = No overvoltage. 1b = Overvoltage.
6	VIN_OV	RC	0b	VIN overvoltage error flag. NOTE: Identical to the VIN_OV bit in the OFF_STATE_L_STAT register. 0b = No overvoltage. 1b = Overvoltage.
5	RESERVED	R	0b	Reserved
4	VREG_OV	RC	0b	VREG overvoltage error flag 0b = No overvoltage. 1b = Overvoltage.
3	BOOST_OV	RC	0b	BOOST overvoltage error flag 0b = No overvoltage. 1b = Overvoltage.
2	RESERVED	R	0b	Reserved
1	BUCK2_OV	RC	0b	BUCK2 overvoltage error flag 0b = No overvoltage. 1b = Overvoltage.
0	BUCK1_OV	RC	0b	BUCK1 overvoltage error flag 0b = No overvoltage. 1b = Overvoltage.

EXT_VMON_STAT Register

EXT_VMON_STAT is shown in Figure 11-59 and described in Table 11-46.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_EXT_VMON_STAT)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.
EXT VMON UV/OV monitoring is active only when EXT VMON-s is enabled. When EXT VMON-s are disabled UV/OV monitoring is masked.

Figure 11-59 External VMON Status (EXT_VMON_STAT) Register

7	6	5	4	3	2	1	0
RESERVED		EXT_VMON2_OV	EXT_VMON2_UV	RESERVED		EXT_VMON1_OV	EXT_VMON1_UV
R-00b		RC-0b	RC-0b	R-00b		RC-0b	RC-0b

Table 11-46 EXT_VMON_STATC Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved.
5	EXT_VMON2_OV	RC	0b	EXT VMON2 overvoltage error flag. 0b = No overvoltage. 1b = Overvoltage.
4	EXT_VMON2_UV	RC	0b	EXT VMON2 undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.
3-2	RESERVED	R	00b	Reserved.
1	EXT_VMON1_OV	RC	0b	EXT VMON1 overvoltage error flag. 0b = No overvoltage. 1b = Overvoltage.
0	EXT_VMON1_UV	RC	0b	EXT VMON1 undervoltage error flag. 0b = No undervoltage. 1b = Undervoltage.

SAFETY_BUCK1_STAT1 Register

SAFETY_BUCK1_STAT1 is shown in Figure 11-60 and described in Table 11-47.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_BUCK1_STAT1)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-60 Safety BUCK1 Status 1 (SAFETY_BUCK1_STAT1) Register

7	6	5	4	3	2	1	0
RESERVED		BUCK1_EOVP	BUCK1_PGND_LOSS	BUCK1_OVP	BUCK1_LS_SINK_OVC	BUCK1_LS_OVC	BUCK1_SCG
R-00b		RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-47 SAFETY_BUCK1_STAT1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved.
5	BUCK1_EOVP	RC	0b	BUCK1 extreme overvoltage protection status flag. 0b = No extreme overvoltage protection. 1b = Extreme overvoltage protection.
4	BUCK1_PGND_LOSS	RC	0b	BUCK1 Loss of PGND status flag. 0b = No BUCK1 Loss-of-PGND. 1b = BUCK1 Loss-of-GND.
3	BUCK1_OVP	RC	0b	BUCK1 overvoltage protection status flag. 0b = No overvoltage protection. 1b = Overvoltage protection.
2	BUCK1_LS_SINK_OVC	RC	0b	BUCK1 LS sink current limit error flag. 0b = No BUCK1 LS sink current limit. 1b = BUCK1 LS sink current limit.
1	BUCK1_OVC	RC	0b	BUCK1 overload error flag. 0b = No overload condition. 1b = Overload condition.
0	BUCK1_SCG	RC	0b	BUCK1 short-circuit to ground error flag. 0b = No short-circuit condition. 1b = Short-circuit condition.

SAFETY_BUCK1_STAT2 Register

SAFETY_BUCK1_STAT2 is shown in Figure 11-61 and described in Table 11-48.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_BUCK1_STAT2)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-61 Safety BUCK1 Status 2 (SAFETY_BUCK1_STAT2) Register

7	6	5	4	3	2	1	0
RESERVED						BUCK1_OT_STD	BUCK1_OT_WARN
R-000000b						RC-0b	RC-0b

Table 11-48 SAFETY_BUCK1_STAT2 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-2	RESERVED	R	000000b	Reserved.
1	BUCK1_OT_STD	RC	0b	BUCK1 overtemperature shutdown flag. 0b = No overtemperature shutdown. 1b = Overtemperature shutdown.
0	BUCK1_OT_WARN	RC	0b	BUCK1 overtemperature warning flag. 0b = No overtemperature warning. 1b = Overtemperature warning.

Bit

Field

Type

Initial State

Description

7-2

RESERVED

R

000000b

Reserved.

1

BUCK1_OT_STD

RC

0b

BUCK1 overtemperature shutdown flag.

0b = No overtemperature shutdown.

1b = Overtemperature shutdown.

0

BUCK1_OT_WARN

RC

0b

BUCK1 overtemperature warning flag.

0b = No overtemperature warning.

1b = Overtemperature warning.

SAFETY_BUCK2_STAT1 Register

SAFETY_BUCK2_STAT1 is shown in Figure 11-62 and described in Table 11-49.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_BUCK2_STAT1)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-62 Safety BUCK2 Status 1 (SAFETY_BUCK2_STAT1) Register

7	6	5	4	3	2	1	0
RESERVED			BUCK2_PGND_LOSS	BUCK2_OVP	BUCK2_LS_SINK_OVC	BUCK2_LS_OVC	BUCK2_SCG
R-000b			RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-49 SAFETY_BUCK2_STAT1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-5	RESERVED	R	000b	Reserved.
4	BUCK2_PGND_LOSS	RC	0b	BUCK2 Loss of PGND status flag. 0b = No BUCK2 Loss-of-PGND. 1b = BUCK2 Loss-of-GND.
3	BUCK2_OVP	RC	0b	BUCK2 overvoltage protection status flag. 0b = No overvoltage protection. 1b = Overvoltage protection.
2	BUCK2_LS_SINK_OVC	RC	0b	BUCK2 LS sink current limit error flag. 0b = No BUCK2 LS sink current limit. 1b = BUCK2 LS sink current limit.
1	BUCK2_LS_OVC	RC	0b	BUCK2 overload error flag. 0b = No overload condition. 1b = Overload condition.
0	BUCK2_SCG	RC	0b	BUCK2 short-circuit to ground error flag. 0b = No short-circuit condition. 1b = Short-circuit condition.

SAFETY_BUCK2_STAT2 Register

SAFETY_BUCK2_STAT2 is shown in Figure 11-63 and described in Table 11-50.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_BUCK2_STAT2)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-63 Safety BUCK2 Status 2 (SAFETY_BUCK2_STAT2) Register

7	6	5	4	3	2	1	0
RESERVED						BUCK2_OT_STD	BUCK2_OT_WARN
R-000000b						RC-0b	RC-0b

Table 11-50 SAFETY_BUCK2_STAT2 Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-2

RESERVED

R

000000b

Reserved.

1

BUCK2_OT_STD

RC

0b

BUCK2 overtemperature shutdown flag.

0b = No overtemperature shutdown.

1b = Overtemperature shutdown.

0

BUCK2_OT_WARN

RC

0b

BUCK2 overtemperature warning flag.

0b = No overtemperature warning.

1b = Overtemperature warning.

SAFETY_BOOST_STAT1 Register

SAFETY_BOOST_STAT1 is shown in and described in Figure 11-64 and described in Table 11-51.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_BOOST_STAT1)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-64 Safety BOOST Status 1 (SAFETY_BOOST_STAT1) Register

7	6	5	4	3	2	1	0
RESERVED			BOOST_PGND_LOSS	BOOST_OVP	BOOST_HS_SINK_OVC	BOOST_HS_OVC	BOOST_SCG
R-000b			RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-51 SAFETY_BOOST_STAT1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-5	RESERVED	R	000b	Reserved
4	BOOST_PGND_LOSS	RC	0b	BOOST Loss of PGND status flag. 0b = No BOOST Loss-of-PGND. 1b = BOOST Loss-of-GND.
3	BOOST_OVP	RC	0b	BOOST overvoltage protection status flag. 0b = No overvoltage protection. 1b = Overvoltage protection.
2	BOOST_HS_SINK_OVC	RC	0b	BOOST HS sink current limit error flag. 0b = No BOOST HS sink current limit. 1b = BOOST HS sink current limit.
1	BOOST_HS_OVC	RC	0b	BOOST overload error flag. 0b = No overload condition. 1b = Overload condition.
0	BOOST_SCG	RC	0b	BOOST short-circuit to ground error flag. 0b = No short-circuit condition. 1b = Short-circuit condition.

SAFETY_BOOST_STAT2 Register

SAFETY_BOOST_STAT2 is shown in and described in Figure 11-65 and described in Table 11-52.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ BOOST _STAT2)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-65 Safety BOOST Status 2 (SAFETY_BOOST_STAT2) Register

7	6	5	4	3	2	1	0
RESERVED						BOOST_OT_STD	BOOST_OT_WARN
R-000000b						RC-0b	RC-0b

Table 11-52 SAFETY_BOOST_STAT2 Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-2

RESERVED

R

000000b

Reserved.

1

BOOST_OT_STD

RC

0b

BOOST overtemperature shutdown flag.

0b = No overtemperature shutdown.

1b = Overtemperature shutdown.

0

BOOST_OT_WARN

RC

0b

BOOST overtemperature warning flag.

0b = No overtemperature warning.

1b = Overtemperature warning.

SAFETY_ERR_STAT1 Register

SAFETY_ERR_STAT1 is shown in and described in Figure 11-66 and described in Table 11-53.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ERR_STAT1)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-66 Safety Error Status 1 (SAFETY_ERR_STAT1) Register

7	6	5	4	3	2	1	0
RESERVED		DEV_CFG_CRC_ERR	EE_CRC_ERR	NRES_ERR	ENDRV_nIRQ_DRV_ERR	SPI_ERR[1:0]
R-00b		RC-0b	RC-0b	RC-0b	RC-0b	RC-00b

Table 11-53 SAFETY_ERR_STAT1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved.
5	DEV_CFG_CRC_ERR	RC	0b	CRC error flag for the device configuration registers. This bit is set to 1b when calculated CRC8 value for device-configuration registers does not match expected CRC8 value stored in the SAFETY_DEV_CFG_CRC register. 0b = No CRC error. 1b = CRC error.
4	EE_CRC_ERR	RC	0b	CRC error flag for EEPROM registers. This bit is set to 1b when calculated CRC8 value for EEPROM registers does not match internally programmed CRC8 value. 0b = No CRC error. 1b = CRC error.
3	NRES_ERR	RC	0b	The NRES driver read-back error flag. 0b = No read-back error. 1b = Read-back error.
2	ENDRV_nIRQ_DRV_ERR	RC	0b	The ENDRV/nIRQ driver read-back error flag. 0b = No read-back error. 1b = Read-back error.
1-0	SPI_ERR[1:0]	RC	00b	SPI Error flags. NOTE: if a reset to the MCU is asserted during a SPI frame transfer (causing a truncated SPI frame), these SPI Error Status bits will not be cleared, but will keep the status according to the truncated previous SPI frame until SPI Read access to this register. 00b = No error. 01b = Command error. 10b = Format error (received bit count not equal to 24 or 16). 11b = Data output mismatch.

SAFETY_CLK_STAT Register

SAFETY_CLK_STAT is shown in and described in Figure 11-67 and described in Table 11-54.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_CLK_STAT)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-67 Safety Clock Status (SAFETY_CLK_STAT) Register

7	6	5	4	3	2	1	0
SYSCLK_ERR	BOOST_FSW_CLK_ERR	RESERVED	BUCK2_FSW_CLK_ERR	BUCK1_FSW_CLK_ERR	SYNC_CLK_ERR	SMPS_SRC_CLK_ERR	DIG_SYSCLK_ERR
RC-0b	RC-0b	R-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-54 SAFETY_CLK_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	SYSCLK_ERR	RC	0b	8-MHz system clock error flag from either the analog clock monitor or the digital clock monitor. NOTE: This bit is a replica of bit 2 in OFF_STATE_L_STAT register, and is cleared after read access to this register. 0b = No System Clock error. 1b = System Clock error.
6	BOOST_FSW_CLK_ERR	RC	0b	Clock error flag from DIG_CLK_MON5 for BOOST switching clock. 0b = No clock error. 1b = Clock error.
5	RESERVED	R	0b	Reserved.
4	BUCK2_FSW_CLK_ERR	RC	0b	Clock error flag from DIG_CLK_MON4 for BUCK2 switching clock. 0b = No clock error. 1b = Clock error.
3	BUCK1_FSW_CLK_ERR	RC	0b	Clock error flag from DIG_CLK_MON3 for BUCK1 switching clock . 0b = No clock error. 1b = Clock error.
2	SYNC_CLK_ERR	RC	0b	Clock error flag from DIG_CLK_MON1 for SYNC_IN clock input. 0b = No clock error. 1b = Clock error.
1	SMPS_SRC_CLK_ERR	RC	0b	Clock error flag from DIG_CLK_MON6 for either PLL clock output or MODCLK output. 0b = No clock error. 1b = Clock error.
0	DIG_SYSCLK_ERR	RC	0b	DIG_SYSCLK_ERR error / fault reaction by the device state machine is masked/disabled in device EEPROM and this has no impact to device overall functionality. Ignore, if this bit is set.

SAFETY_CLK_WARN_STAT Register

SAFETY_CLK_WARN_STAT is shown in and described in Figure 11-68 and described in Table 11-55.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_CLK_WARN_STAT)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-68 Safety Clock Warning Status (SAFETY_CLK_WARN_STAT) Register

7	6	5	4	3	2	1	0
RESERVED	BOOST_FSW_CLK_WARN	RESERVED	BUCK2_FSW_CLK_WARN	BUCK1_FSW_CLK_WARN	SYNC_CLK_WARN	SMPS_SRC_CLK_WARN	RESERVED
R-0b	RC-0b	R-0b	RC-0b	RC-0b	RC-0b	RC-0b	R-0b

Table 11-55 SAFETY_CLK_WARN_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	BOOST_FSW_CLK_WARN	RC	0b	Clock accuracy warning flag from DIG_CLK_MON5 for BOOST switching clock. 0b = No clock warning. 1b = Clock warning.
5	RESERVED	R	0b	Reserved
4	BUCK2_FSW_CLK_WARN	RC	0b	Clock accuracy warning flag from DIG_CLK_MON4 for BUCK2 switching clock. 0b = No clock warning. 1b = Clock warning.
3	BUCK1_FSW_CLK_WARN	RC	0b	Clock accuracy warning flag from DIG_CLK_MON3 for BUCK1 switching clock. 0b = No clock warning. 1b = Clock warning.
2	SYNC_CLK_WARN	RC	0b	Clock accuracy warning flag from DIG_CLK_MON1 for SYNC_IN clock. 0b = No clock warning. 1b = Clock warning.
1	SMPS_SRC_CLK_WARN	RC	0b	Clock accuracy warning flag from DIG_CLK_MON6 for either PLL clock output or MODCLK output. 0b = No clock warning. 1b = Clock warning.
0	RESERVED	R	0b	Reserved.

SAFETY_ABIST_ERR_STAT1 Register

SAFETY_ABIST_ERR_STAT1 is shown in and described in Figure 11-69 and described in Table 11-56.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ABIST_ERR_STAT1)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-69 Safety ABIST Error Status 1 (SAFETY_ABIST_ERR_STAT1) Register

7	6	5	4	3	2	1	0
ABIST_GROUP4_ERR	ABIST_GROUP3_ERR	ABIST_GROUP2_ERR	ABIST_GROUP1_ERR	ABIST_GROUP4_DONE	ABIST_GROUP3_DONE	ABIST_GROUP2_DONE	ABIST_GROUP1_DONE
RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-56 SAFETY_ABIST_ERR_STAT1 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	ABIST_GROUP4_ERR	RC	0b	ABIST Group 4 error flag. 0b = No ABIST Group 4 error. 1b = ABIST Group 4 error.
6	ABIST_GROUP3_ERR	RC	0b	ABIST Group 3 error flag. 0b = No ABIST Group 3 error. 1b = ABIST Group 3 error.
5	ABIST_GROUP2_ERR	RC	0b	ABIST Group 2 error flag. 0b = No ABIST Group 2 error. 1b = ABIST Group 2 error.
4	ABIST_GROUP1_ERR	RC	0b	ABIST Group 1 error flag. 0b = No ABIST Group 1 error. 1b = ABIST Group 1 error.
3	ABIST_GROUP4_DONE	RC	0b	ABIST Group 4 completion status flag. 0b = ABIST Group 4 is not completed. 1b = ABIST Group 4 is completed.
2	ABIST_GROUP3_DONE	RC	0b	ABIST Group 3 completion status flag. 0b = ABIST Group 3 is not completed. 1b = ABIST Group 3 is completed.
1	ABIST_GROUP2_DONE	RC	0b	ABIST Group 2 completion status flag. 0b = ABIST Group 2 is not completed. 1b = ABIST Group 2 is completed.
0	ABIST_GROUP1_DONE	RC	0b	ABIST Group 1 completion status flag. 0b = ABIST Group 1 is not completed. 1b = ABIST Group 1 is completed.

SAFETY_ABIST_ERR_STAT2 Register

SAFETY_ABIST_ERR_STAT2 is shown in and described in Figure 11-70 and described in Table 11-57.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ABIST_ERR_STAT2)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-70 Safety ABIST Error Status 2 (SAFETY_ABIST_ERR_STAT2) Register

7	6	5	4	3	2	1	0
ABIST_VREG_UV_ERR	RESERVED	ABIST_EXTVMON2_UV_ERR	ABIST_EXTVMON1_UV_ERR	ABIST_BOOST_UV_ERR	RESERVED	ABIST_BUCK2_UV_ERR	ABIST_BUCK1_UV_ERR
RC-0b	R-0b	RC-0b	RC-0b	RC-0b	R-0b	RC-0b	RC-0b

Table 11-57 SAFETY_ABIST_ERR_STAT2 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	ABIST_VREG_UV_ERR	RC	0b	ABIST on VREG UV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
6	RESERVED	R	0b	Reserved.
5	ABIST_EXTVMON2_UV_ERR	RC	0b	ABIST on EXT VMON2 UV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
4	ABIST_EXTVMON1_UV_ERR	RC	0b	ABIST on EXT VMON1 UV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
3	ABIST_BOOST_UV_ERR	RC	0b	ABIST on BOOST UV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
2	RESERVED	R	0b	Reserved.
1	ABIST_BUCK2_UV_ERR	RC	0b	ABIST on BUCK2 UV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
0	ABIST_BUCK1_UV_ERR	RC	0b	ABIST on BUCK2 UV comparator error flag. 0b = No ABIST error. 1b = ABIST error.

SAFETY_ABIST_ERR_STAT3 Register

SAFETY_ABIST_ERR_STAT3 is shown in and described in Figure 11-71 and described in Table 11-58.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ABIST_ERR_STAT3)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-71 Safety ABIST Error Status 3 (SAFETY_ABIST_ERR_STAT3) Register

7	6	5	4	3	2	1	0
ABIST_VREG_OV_ERR	RESERVED	ABIST_EXTVMON2_OV_ERR	ABIST_EXTVMON1_OV_ERR	ABIST_BOOST_OV_ERR	RESERVED	ABIST_BUCK2_OV_ERR	ABIST_BUCK1_OV_ERR
RC-0b	R-0b	RC-0b	RC-0b	RC-0b	R-0b	RC-0b	RC-0b

Table 11-58 SAFETY_ABIST_ERR_STAT3 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	ABIST_VREG_OV_ERR	RC	0b	ABIST on VREG OV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
6	RESERVED	R	0b	Reserved.
5	ABIST_EXTVMON2_OV_ERR	RC	0b	ABIST on EXT VMON2 OV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
4	ABIST_EXTVMON1_OV_ERR	RC	0b	ABIST on EXT VMON1 OV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
3	ABIST_BOOST_OV_ERR	RC	0b	ABIST on BOOST OV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
2	RESERVED	R	0b	Reserved.
1	ABIST_BUCK2_OV_ERR	RC	0b	ABIST on BUCK2 OV comparator error flag. 0b = No ABIST error. 1b = ABIST error.
0	ABIST_BUCK1_OV_ERR	RC	0b	ABIST on BUCK1 OV comparator error flag. 0b = No ABIST error. 1b = ABIST error.

SAFETY_ABIST_ERR_STAT4 Register

SAFETY_ABIST_ERR_STAT4 is shown in and described in Figure 11-72 and described in Table 11-59.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ABIST_ERR_STAT4)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-72 Safety ABIST Error Status 4 (SAFETY_ABIST_ERR_STAT4) Register

7	6	5	4	3	2	1	0
ABIST_BOOST_CL_ERR	RESERVED	ABIST_BUCK2_CL_ERR	ABIST_BUCK1_CL_ERR	ABIST_BOOST_OVP_ERR	RESERVED	ABIST_BUCK2_OVP_ERR	ABIST_BUCK1_OVP_ERR
RC-0b	R-0b	RC-0b	RC-0b	RC-0b	R-0b	RC-0b	RC-0b

Table 11-59 SAFETY_ABIST_ERR_STAT4 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	ABIST_BOOST_CL_ERR	RC	0b	ABIST on BOOST current limit comparator error flag. 0b = No ABIST error. 1b = ABIST error.
6	RESERVED	R	0b	Reserved.
5	ABIST_BUCK2_CL_ERR	RC	0b	ABIST on BUCK2 current limit comparator error flag. 0b = No ABIST error. 1b = ABIST error.
4	ABIST_BUCK1_CL_ERR	RC	0b	ABIST on BUCK1 current limit comparator error flag. 0b = No ABIST error. 1b = ABIST error.
3	ABIST_BOOST_OVP_ERR	RC	0b	ABIST on BOOST OVP comparator error flag. 0b = No ABIST error. 1b = ABIST error.
2	RESERVED	R	0b	Reserved.
1	ABIST_BUCK2_OVP_ERR	RC	0b	ABIST on BUCK2 OVP comparator error flag. 0b = No ABIST error. 1b = ABIST error.
0	ABIST_BUCK1_OVP_ERR	RC	0b	ABIST on BUCK1 OVP comparator error flag. 0b = No ABIST error. 1b = ABIST error.

SAFETY_ABIST_ERR_STAT5 Register

SAFETY_ABIST_ERR_STAT5 is shown in and described in Figure 11-73 and described in Table 11-60.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ABIST_ERR_STAT5)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-73 Safety ABIST Error Status 5 (SAFETY_ABIST_ERR_STAT5) Register

7	6	5	4	3	2	1	0
RESERVED			ABIST_EE_CRC_MON_ERR	ABIST_BOOST_OT_ERR	RESERVED	ABIST_BUCK2_OT_ERR	ABIST_BUCK1_OT_ERR
R-000b			RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-60 SAFETY_ABIST_ERR_STAT5 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-5	RESERVED	R	000b	Reserved.
4	ABIST_EE_CRC_MON_ERR	RC	0b	ABIST on EEPROM CRC monitor error. 0b = No ABIST error. 1b = ABIST error.
3	ABIST_BOOST_OT_ERR	RC	0b	ABIST on BOOST OT monitor error. 0b = No ABIST error. 1b = ABIST error.
2	RESERVED	R	0b	Reserved.
1	ABIST_BUCK2_OT_ERR	RC	0b	ABIST on BUCK2 OT monitor error. 0b = No ABIST error. 1b = ABIST error.
0	ABIST_BUCK1_OT_ERR	RC	0b	ABIST BUCK1 OT monitor error. 0b = No ABIST error. 1b = ABIST error.

SAFETY_ABIST_ERR_STAT6 Register

SAFETY_ABIST_ERR_STAT6 is shown in and described in Figure 11-74 and described in Table 11-61.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ABIST_ERR_STAT6)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-74 Safety ABIST Error Status 6 (SAFETY_ABIST_ERR_STAT6) Register

7	6	5	4	3	2	1	0
RESERVED	ABIST_DSYSCLK_MON_ERR	ABIST_FSW3_CLK_MON_ERR	ABIST_FSW2_CLK_MON_ERR	ABIST_FSW1_CLK_MON_ERR	ABIST_PLL_CLK_MON_ERR	ABIST_SYNC_CLK_MON_ERR	ABIST_ACLK_MON_ERR
R-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-61 SAFETY_ABIST_ERR_STAT6 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	Reserved	R	0b	Reserved.
6	ABIST_DSYSCLK_MON_ERR	RC	0b	ABIST on digital system clock monitor (DIG_CLK_MON2) error. 0b = No ABIST error. 1b = ABIST error.
5	ABIST_FSW3_CLK_MON_ERR	RC	0b	ABIST on BOOST switching clock monitor (DIG_CLK_MON5) error. 0b = No ABIST error. 1b = ABIST error.
4	ABIST_FSW2_CLK_MON_ERR	RC	0b	ABIST on BUCK2 switching clock monitor (DIG_CLK_MON4) error. 0b = No ABIST error. 1b = ABIST error.
3	ABIST_FSW1_CLK_MON_ERR	RC	0b	ABIST on BUCK1 switching clock monitor (DIG_CLK_MON3) error. 0b = No ABIST error. 1b = ABIST error.
2	ABIST_PLL_CLK_MON_ERR	RC	0b	ABIST on the SMPS source clock monitor (DIG_CLK_MON6) error. 0b = No ABIST error. 1b = ABIST error.
1	ABIST_SYNC_CLK_MON_ERR	RC	0b	ABIST on SYNC_IN input clock monitor (DIG_CLK_MON1) error. 0b = No ABIST error. 1b = ABIST error.
0	ABIST_ACLK_ MON_ERR	RC	0b	ABIST on analog system clock monitor error. 0b = No ABIST error. 1b = ABIST error.

SAFETY_LBIST_ERR_STAT Register

SAFETY_LBIST_ERR_STAT is shown in and described in Figure 11-75 and described in Table 11-62.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_LBIST_ERR_STAT)
Note: A

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.
The Watchdog, NRES supervisor, MCU error signal monitoring diagnostics are covered by LBIST core test.

Figure 11-75 Safety LBIST Error Status (SAFETY_LBIST_ERR_STAT) Register

7	6	5	4	3	2	1	0
RESERVED	DEV_CFG_CRC_DIAG_ERR	EE_CRC_DIAG_ERR	NRES_ERR_DIAG_ERR	ENDRV/nIRQ _DIAG_ERR	LBIST_DIAG_ERR	LBIST_CORE_ERR	LBIST_DONE
R-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-62 SAFETY_LBIST_ERR_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	DEV_CFG_CRC_DIAG_ERR	RC	0b	Device configuration register CRC8 diagnostic error flag. 0b = No diagnostic error. 1b = Diagnostic error.
5	EE_CRC_DIAG_ERR	RC	0b	EEPROM CRC8 diagnostic error flag. 0b = No diagnostic error. 1b = Diagnostic error.
4	NRES_ERR_DIAG_ERR	RC	0b	NRES error monitor diagnostic error flag. 0b = No diagnostic error. 1b = Diagnostic error.
3	ENDRV/nIRQ _DIAG_ERR	RC	0b	ENDRV/nIRQ diagnostic error flag. 0b = No diagnostic error. 1b = Diagnostic error.
2	LBIST_DIAG_ERR	RC	0b	LBIST diagnostic run error. 0b = No diagnostic error. 1b = Diagnostic error.
1	LBIST_CORE_ERR	RC	0b	LBIST core error flag. 0b = No LBIST core error. 1b = LBIST core error.
0	LBIST_DONE	RC	0b	LBIST completion status flag. 0b = LBIST not completed. 1b = LBIST completed.

SAFETY_ERR_STAT2 Register

SAFETY_ERR_STAT2 is shown in and described in Figure 11-76 and described in Table 11-63.

Return to Table 11-23

Initialization source: NPOR, RESET, SPI RD Access, LBIST run, WD_CFG change
Controller access: Read (RD_SAFETY_ERR_STAT2)
Write (WR_WD_FC) for the WD_FAIL_CNT bits write access only. The write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-76 Safety Error Status 2 (SAFETY_ERR_STAT2) Register

7	6	5	4	3	2	1	0
RESERVED	WD_RST_FAIL	WD_ENDRV_FAIL	WD_FAIL	WD_FAIL_CNT[3:0]
R-0b	RC-0b	RC-1b	RC-0b	R/W-X

Table 11-63 SAFETY_ERR_STAT2 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	WD_RST_FAIL	RC	0b	Watchdog reset failure flag. NOTE: This flag bit is not cleared by RESET event so that MCU can confirm that previous system reset was caused by watchdog failure as the device enters the DIAGNOSTIC state. This bit will get set regardless of WD_RST_EN bit setting. 0b = WD_FAIL_CNT < WD_FC_RST_TH 1b = WD_FAIL_CNT ≥ WD_FC_RST_TH
5	WD_ENDRV_FAIL	RC	1b	Watchdog ENDRV failure flag. 0b = WD_FAIL_CNT < WD_FC_ENDRV_TH 1b = WD_FAIL_CNT ≥ WD_FC_ ENDRV_TH
4	WD_FAIL	RC	0b	Watchdog failure flag that is set each time watchdog ‘bad event’ occurs, accompanied by the WD_FAIL_CNT increment. 0b = No watchdog failure. 1b = Watchdog failure.
3-0	WD_FAIL_CNT[3:0]	R/W	X	State of the watchdog failure counter. NOTE: The default value (X) is set by the WD_FC_ENDRV_TH[3:0] bits.

SAFETY_ERR_STAT3 Register

SAFETY_ERR_STAT3 is shown in and described in Figure 11-77 and described in Table 11-64.

Return to Table 11-23

Initialization source: NPOR, REST, SPI RD Access, LBIST run, MCU_ESM_CFG bit change
Controller access: Read (RD_SAFETY_ERR_STAT3)
Write (WR_MCU_ESM_FC). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Write access only for the MCU_ESM_FC bits.
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-77 Safety Error Status 3 (SAFETY_ERR_STAT3) Register

7	6	5	4	3	2	1	0
RESERVED	MCU_ESM_RST_FAIL	MCU_ESM_ENDRV_FAIL	MCU_ESM_FAIL	MCU_ESM_FC[3:0]
R-0b	RC-0b	RC-0b	RC-0b	R/W-0101b

Table 11-64 SAFETY_ERR_STAT3 Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	RESERVED	R	0b	Reserved.
6	MCU_ESM_RST_FAIL	RC	0b	MCU ESM error flag. 0b = WD_FAIL_CNT < WD_FC_ENDRV_TH 1b = MCU_ESM_FC ≥ MCU_ESM_FC_RST_TH
5	MCU_ESM_ENDRV_FAIL	RC	0b	MCU ESM error flag. 0b = MCU_ESM_FC < MCU_ESM_FC_ENDRV_TH 1b = MCU_ESM_FC ≥ MCU_ESM_FC_ENDRV_TH
4	MCU_ESM_FAIL	RC	0b	MCU ESM failure flag that is set each time the ESM detects a failure, accompanied by the MCU_ESM_FC increment. 0b = No MCU ESM failure. 1b = MCU ESM failure detected.
3-0	MCU_ESM_FC[3:0]	R/W	0101b	State of the MCU ESM failure counter. - The default value is 5, and is initialized to this value upon entering the RESET state, DIAGNOSTIC State, after LBIST completion, anytime MCU_ESM_CFG bit toggles (when changing MCU ESM configuration mode) and after MCU_ESM_EN bit (bit D2 in SAFETY_CHECK_CTRL register) toggles from 0 to 1. - The MCU_ESM_FC increments by 1 every time MCU ESM error is detected and decrements by 1 each time correct response is received. When MCU_ESM_FC ≥ MCU_ESM_FC_ENDRV_TH, the MCU_ESM_FAIL bit and MCU_ESM_ENDRV_FAIL bit are set to 1b, and if device is in the ACTIVE State or DIAGNOSTIC state the device transitions to the SAFE state. When MCU_ESM_FC ≥ MCU_ESM_FC_RST_TH, the MCU_ESM_FAIL bit and MCU_ESM_RST_FAIL bit are set to 1b, and if device is in the ACTIVE or DIAGNOSTIC state device transitions to the RESET state.

SAFETY_ERR_STAT4 Register

SAFETY_ERR_STAT4 is shown in and described in Figure 11-78 and described in Table 11-65.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SAFETY_ERR_STAT4)
Write (WR_DEV_ERR_CNT). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Write access only for DEV_ERR_CNT bits.
Note:

A logic high is latched for DIAG_STATE_TO until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.

Figure 11-78 Safety Error Status 4 (SAFETY_ERR_STAT4) Register

7	6	5	4	3	2	1	0
RESERVED			DIAG_STATE_TO	DEV_ERR_CNT[3:0]
R-0b			RC-0b	R/W-0000b

Table 11-65 SAFETY_ERR_STAT4 Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-5

Reserved

R

0b

Reserved

4

DIAG_STATE_TO

R/W

0b

Bit is set to 1b when the DIAGNOSTIC state time-out event is detected. This event causes the device to transition from the DIAGNOSTIC to the SAFE state and increments DEV_ERR_CNT by 1.
This bit gets cleared to 0 upon MCU read-out.

3-0

DEV_ERR_CNT[3:0]

R/W

0b

State of the device error counter.
NOTE:

The counter value increments by 1 when the device transitions to the SAFE state from the DIAGNOSTIC or ACTIVE state. It does not increments when the device transitions from the RESET state to the SAFE state while DEV_ERR_CNT > SAFE_LOCK_TH.
The bit can be overwritten by SPI WR access, but only in the DIAGNOSTIC state when CFG_LOCK = 0.
When DEV_ERR_CNT = PWD_TH, the device transitions to the OFF state, and wakes-up on new wake-up event.

SPI_TRANSFER_STAT Register

SPI_TRANSFER_STAT is shown in and described in Figure 11-79 and described in Table 11-66.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_SPI_TRANSFER_STAT)
Note:

A logic high is latched until the register is read.
The read access clears set status flag bit if condition is not present anymore. Another read access is required to confirm status bit has been cleared and monitored condition is not present anymore.
These SPI transfer status bits reflect state of previous SPI frame transfer.

Figure 11-79 SPI Transfer Status (SPI_TRANSFER_STAT) Register

7	6	5	4	3	2	1	0
SPI_SDO_ERR	SPI_SHORT_FRAME	SPI_LONG_FRAME	SPI_INVALID_UNDEF_CMD	SPI_SDI_CRC_ERR	SPI_CLK_CS_ERR2	SPI_CLK_CS_ERR1	SPI_RESET_TERM
RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-66 SPI_TRANSFER_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	SPI_SDO_ERR	RC	0b	SPI SDO error (mismatch between SPI driver output and feedback input) flag. 0b = No SPI SDO error. 1b = SPI SDO error.
6	SPI_SHORT_FRAME	RC	0b	SPI short frame error flag. The frame contains less than 24 SPI rising, falling clock cycles, or both. 0b = No SPI short frame error. 1b = SPI short frame error.
5	SPI_LONG_FRAME	RC	0b	SPI long frame error flag. The frame contain more than 24 SPI rising, falling clock cycles, or both. 0b = No SPI long frame error. 1b = SPI long frame error.
4	SPI_INVALID_UNDEF_CMD	RC	0b	SPI command error flag due to invalid or undefined SPI Command. 0b = No SPI command error. 1b = SPI command error.
3	SPI_SDI_CRC_ERR	RC	0b	SPI CRC error flag on received SPI frame. 0b = No SPI CRC error. 1b = SPI CRC error.
2	SPI_CLK_CS_ERR2	R/C	0b	SPI clock input error (high on SPI Chip Select high-to-low transition) flag. 0b = No SPI clock error. 1b = SPI clock error.
1	SPI_CLK_CS_ERR1	RC	0b	SPI clock input error (high on SPI Chip Select low-to-high transition) flag. 0b = No SPI clock error. 1b = SPI clock error.
0	SPI_RESET_TERM	RC	0b	SPI transfer error flag due to termination by RESET event. 0b = No SPI transfer terminated by RESET event. 1b = SPI transfer terminated by RESET event.

SAFETY_ABIST_CTRL Register

SAFETY_ABIST_CTRL is shown in and described in Figure 11-80 and described in Table 11-67.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_SAFETY_ABIST_CTRL)
Write (WR_SAFETY_ABIST_CTRL). Write access is only available when the CTRL_BIST_LOCK bit is set to 0b.

Figure 11-80 Safety ABIST Control (SAFETY_ABIST_CTRL) Register

7	6	5	4	3	2	1	0
RESERVED				ABIST_GROUP4_START	ABIST_GROUP3_START	ABIST_GROUP2_START	ABIST_GROUP1_START
R-0000b				R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 11-67 SAFETY_ABIST_CTRL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	RESERVED	R	0000b	Reserved.
3	ABIST_GROUP4_START	R/W	0b	Initiates ABIST Group 4 of tests. Once ABIST is completed, the ABIST_GROUP4_DONE status bit is set in the SAFETY_ABIST_ERR_STAT1 register, the ABIST_GROUP4_ERR status bits is set if any of ABIST Group 4 of tests failed. The bit is self-cleared unless the ABIST scheduler is enabled in the ACTIVE state.
2	ABIST_GROUP3_START	R/W	0b	Initiates ABIST Group 3 of tests. Once ABIST is completed, the ABIST_GROUP3_DONE status bit is set in the SAFETY_ABIST_ERR_STAT1 register, the ABIST_GROUP3_ERR status bits is set if any of ABIST Group 3 of tests failed. The bit is self-cleared unless the ABIST scheduler is enabled in the ACTIVE state.
1	ABIST_GROUP2_START	R/W	0b	Initiates ABIST Group 2 of tests. Once ABIST is completed, the ABIST_GROUP2_DONE status bit is set in the SAFETY_ABIST_ERR_STAT1 register, the ABIST_GROUP2_ERR status bits is set if any of ABIST Group 2 of tests failed. The bit is self-cleared unless the ABIST scheduler is enabled in the ACTIVE state.
0	ABIST_GROUP1_START	R/W	0b	Initiates ABIST Group 1 of tests. Once ABIST is completed, the ABIST_GROUP1_DONE status bit is set in the SAFETY_ABIST_ERR_STAT1 register, the ABIST_GROUP1_ERR status bits is set if any of ABIST Group 1 of tests failed. The bit is self-cleared unless the ABIST scheduler is enabled in the ACTIVE state.

SAFETY_LBIST_CTRL Register

SAFETY_LBIST_CTRL is shown in and described in Figure 11-81 and described in Table 11-68.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_SAFETY_LBIST_CTRL)
Write (WR_SAFETY_LBIST_CTRL). Write access is only available when the CTRL_BIST_LOCK bit is set to 0b.

Figure 11-81 Safety LBIST Control (SAFETY_LBIST_CTRL) Register

7	6	5	4	3	2	1	0
RESERVED		LBIST_DIAG_EN	CFG_CRC_DIAG_EN	EE_CRC_DIAG_EN	NRES_ERR_DIAG_EN	ENDRV_DIAG_EN nIRQ_DIAG_EN	LBIST_EN
R-00b		R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 11-68 SAFETY_LBIST_CTRL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	RESERVED	R	00b	Reserved.
5	LBIST_DIAG_EN	R/W	0b	Initiates LBIST diagnostic check to confirm LBIST run can detect a failure. It covers LBIST signature check by modifying expected signature value or input data string modification in order to force LBIST error. The self-test status is monitored through bits D0 and D2 in the SAFETY_LBIST_ERR_STAT register. The bit is self-cleared when the LBIST diagnostic test is completed.
4	CFG_CRC_DIAG_EN	R/W	0b	Initiates device configuration CRC8 diagnostic check. The self-test status is monitored through bits D6 in SAFETY_LBIST_ERR_STAT register. The bit is self-cleared when the CRC diagnostic test is completed.
3	EE_CRC_DIAG_EN	R/W	0b	Initiates EEPROM CRC8 diagnostic check. The self-test status is monitored through bits D5 in SAFETY_LBIST_ERR_STAT register. The bit is self-cleared when the CRC diagnostic test is completed. During this diagnostic testing EE_CRC_ERR bit in SAFETY_ERR_STAT1 is set and can be cleared by MCU after successful completion of this diagnostic check.
2	NRES_ERR_DIAG_EN	R/W	0b	Initiates NRES driver error monitor diagnostic check. It checks that NRES driver error monitor can detect mismatch between intended driver state and actual external pin state. The self-test status is monitored through bits D4 in SAFETY_LBIST_ERR_STAT register. The bit is self-cleared when the CRC diagnostic test is completed.
1	ENDRV_DIAG_EN nIRQ_DIAG_EN	R/W	0b	Initiates ENDRV/nIRQ diagnostic check. It checks that ENDRV/nIRQ pin error monitor can detect mismatch between intended driver state and actual external pin state. The self-test status is monitored through bits D3 in SAFETY_LBIST_ERR_STAT register. The bit is self-cleared when the CRC diagnostic test is completed.
0	LBIST_EN	R/W	0b	Initiates LBIST run in the DIAGNOSTIC, the ACTIVE, or the SAFE state. The self-test status is monitored through bits D0 and D1 in the SAFETY_LBIST_ERR_STAT register. If the bit is set to 1b in the DIAGNOSTIC state, the device clears the DIAG_EXIT_MASK bit to 0b and the DIAGNOSTIC state time-out timer continues to run while the LBIST is in progress. To stay in the DIAGNOSTIC State, the MCU must set the DIAG_EXIT_MASK bit to 1b after the LBIST completion. If the bit is set to 1b in the ACTIVE or SAFE state, the device latches the state of ENDRV/nIRQ pin, and releases it after the LBIST completion. The bit is self-cleared when the LBIST run is completed.

SAFETY_CHECK_CTRL Register

SAFETY_CHECK_CTRL is shown in and described in Figure 11-82 and described in Table 11-69.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_SAFETY_CHECK_CTRL)
Write (WR_SAFETY_CHECK_CTRL). Write access is only available when the CTRL_LOCK bit is set to 0b.

Figure 11-82 Safety Check Control (SAFETY_CHECK_CTRL) Register

7	6	5	4	3	2	1	0
RESERVED			CFG_CRC_EN	ENDRV_EN nIRQ_EN	MCU_ESM_EN	RESERVED	DIAG_EXIT
R-000b			R/W-0b	R/W-0b	R/W-0b	R-0b	R/W-0b

Table 11-69 SAFETY_CHECK_CTRL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-5	RESERVED	R	000b	Reserved.
4	CFG_CRC_EN	R/W	0b	Enables and disables CRC8 check on the device configuration registers. It is recommended MCU change device configuration, followed by updating SAFTY_CFG_CRC register before setting this bit to 1b. The CRC8 check runs continuously as long as this bit is set to 1b. 0b = CRC8 disabled. 1b = CRC8 enabled.
3	ENDRV_EN	R/W	0b	Enables and disables the ENDRV/nIRQ output driver. This bit is cleared when device enters the SAFE state. 0b = The ENDRV/nIRQ pin is pulled low. 1b = The ENDRV/nIRQ pin is pulled high only when device is in the ACTIVE state or DIAGNOSTIC state, if the following conditions are all met: — WD_FAIL_CNT < WD_FC_ENDRV_TH — WD_FAIL_CNT < WD_FC_RST_TH — MCU_ESM_FC < MCU_ESM_FC_ENDRV_TH
2	MCU_ESM_EN	R/W	0b	Enabes and disables MCU Error Signal Monitor (ESM). 0b = MCU ESM disabled. 1b = MCU ESM enabled.
1	Reserved	R	0b	Reserved
0	DIAG_EXIT	R/W	0b	Initiate the exit from the DIAGNOSTIC state to ACTIVE state. This bit can be set only in the DIAGNOSTIC state. Anytime the device transitions from the DIAGNOSTIC state this bit is cleared to 0b. When this bit is set to 1b and DIAG_EXIT_MASK bit is set to 0b, the device transitions from the DIAGNOSTIC to the ACTIVE state.

SAFETY_ERR_PWM_HMAX_CFG Register

SAFETY_ERR_PWM_HMAX_CFG is shown in and described in Figure 11-83 and described in Table 11-70.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_ERR_PWM_HMAX_CFG)
Write (WR_SAFETY_ERR_PWM_HMAX_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-83 Safety Error PWM HMAX Configuration (SAFETY_ERR_PWM_HMAX_CFG) Register

7	6	5	4	3	2	1	0
PWMH_MAX[7:0]
R/W-1010 1000b

Table 11-70 SAFETY_ERR_PWM_HMAX_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	PWMH_MAX[7:0]	R/W	1010 1000b	Maximum high-phase duration, t_{PWM_HIGHMAX}, of the signal at the MCU_ERR pin in PWM mode (MCU_ESM_CFG = 1b). t_{PWM_HIGHMAX} is calculated by the following formula: t_{PWM_HIGHMAX} = (PWMH_MAX[7:0] + 1) × 15 µs.

SAFETY_ERR_PWM_HMIN_CFG Register

SAFETY_ERR_PWM_HMIN_CFG is shown in and described in Figure 11-84 and described in Table 11-71.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_ERR_PWM_HMIN_CFG)
Write (WR_SAFETY_ERR_PWM_HMIN_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-84 Safety Error PWM HMIN Configuration (SAFETY_ERR_PWM_HMIN_CFG) Register

7	6	5	4	3	2	1	0
PWMH_MIN[7:0]
R/W-10100111b

Table 11-71 SAFETY_ERR_PWM_HMIN_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	PWMH_MIN[7:0]	R/W	10100111b	Minimum high-phase duration, t_{PWM_HIGHMIN}, of the signal at the MCU_ERR pin in PWM mode (MCU_ESM_CFG = 1b). t_{PWM_HIGHMIN}is calculated by the following formula: t_{PWM_HIGHMIN} = (PWMH_MIN[7:0] + 1) × 15 µs.

SAFETY_ERR_PWM_LMAX_CFG Register

SAFETY_ERR_PWM_LMAX_CFG is shown in and described in Figure 11-85 and described in Table 11-72.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_ERR_PWM_HMIN_CFG)
Write (WR_SAFETY_ERR_PWM_LMAX_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-85 Safety Error PWM LMAX Configuration (SAFETY_ERR_PWM_LMAX_CFG) Register

7	6	5	4	3	2	1	0
PWML_MAX[7:0]
R/W-00111101b

Table 11-72 SAFETY_ERR_PWM_LMAX_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	PWML_MAX[7:0]	R/W	00111101b	Maximum low-phase duration of the signal at the MCU_ERR pin in PWM mode (MCU_ESM_CFG = 1b) or TM570 mode (MCU_ESM_CFG = 0b). t_{XXX_LOWMAX} is calculated by the following formula: t_{PWM_LOWMAX} = (PWML_MAX[7:0] + 1) × 15 µs, if MCU_ESM_CFG = 1 t_{TMS570_LOWMAX} = (PWML_MAX[7:0] + 1) × 5 µs, if MCU_ESM_CFG = 0

SAFETY_ERR_PWM_LMIN_CFG Register

SAFETY_ERR_PWM_LMIN_CFG is shown in and described in Figure 11-86 and described in Table 11-73.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_ERR_PWM_LMIN_CFG)
Write (WR_SAFETY_ERR_PWM_LMIN_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-86 Safety Error PWM LMIN Configuration (SAFETY_ERR_PWM_LMIN_CFG) Register

7	6	5	4	3	2	1	0
PWML_MIN[7:0]
R/W-00111100b

Table 11-73 SAFETY_ERR_PWM_LMIN_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	PWML_MIN[7:0]	R/W	00111100b	Minimum low-phase duration, t_{PWM_HIGHMIN}, of the signal at the MCU_ERR pin in PWM mode (MCU_ESM_CFG = 1b). t_{PWM_LOWMIN}is calculated by the following formula: t_{PWM_LOWMIN} = (PWML_MIN[7:0] + 1) × 15 µs.

SAFETY_PWD_TH_CFG Register

SAFETY_PWD_TH_CFG is shown in and described in Figure 11-87 and described in Table 11-74.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_PWD_TH_CFG)
Write (WR_SAFETY_PWD_TH_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-87 Safety PWD Threshold Configuration (SAFETY_PWD_TH_CFG) Register

7	6	5	4	3	2	1	0
RESERVED			DEV_ERR_CNT_PWD_EN	PWD_TH[3:0]
R-000b			R/W-0b	R/W-1111b

Table 11-74 SAFETY_PWD_TH_CFG Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-5

RESERVED

R

000b

Reserved.

4

DEV_ERR_CNT_PWD_EN

R/W

0b

Enables and disables device transition to the OFF state when DEV_ERR_CNT[3:0] = PWD_TH[3:0].

0b = Transition to the OFF state disabled.

1b = Transition to the OFF state enabled.

3-0

PWD_TH[3:0]

R/W

1111b

Device error count threshold at which value the device transitions to the OFF state.

SAFETY_DEV_CFG_CRC Register

SAFETY_DEV_CFG_CRC is shown in and described in Figure 11-88 and described in Table 11-75.

Return to Table 11-23

Initialization source: NPOR
Controller access: Read (RD_SAFETY_DEV_CFG_CRC)
Write (WR_SAFETY_DEV_CFG_CRC). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b.

Figure 11-88 Safety Device Configuration CRC (SAFETY_DEV_CFG_CRC) Register

7	6	5	4	3	2	1	0
DEV_CFG_CRC[7:0]
R/W-1001 0110b

Table 11-75 SAFETY_DEV_CFG_CRC Register Field Descriptions

Bit

Field

Type

Initial State

Description

7-0

DEV_CFG_CRC[7:0]

R/W

1001 0110b

Expected CRC8 value for the device configuration registers. MCU needs to write calculated CRC8 value for desired device configuration to this register.

NOTE: Initial state value matches CRC8 Value for default device configuration after wake-up from the OFF state.

DIAG_CTRL Register

DIAG_CTRL is shown in and described in Figure 11-89 and described in Table 11-76.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_DIAG_CTRL)
Write (WR_DIAG_CTRL). Write access is only available when the CTRL_LOCK bit is set to 0b.

Figure 11-89 Diagnostic Control (DIAG_CTRL) Register

7	6	5	4	3	2	1	0
MUX_EN	SPI_SDO	MUX_OUT	INT_CON[2:0]			MUX_CFG[1:0]
R/W-0b	R/W-0b	R/W-0b	R/W-000b			R/W-00b

Table 11-76 DIAG_CTRL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	MUX_EN	R/W	0b	Enables and disables the diagnostic MUX output via the DIAG_OUT pin. 0b = Disabled (DIAG_OUT pin in tri-state). 1b = Enabled.
6	SPI_SDO	R/W	0b	SPI SDO interconnect control for SDO diagnostics. The state of the SDO pin is controlled by this bit when the NCS pin is pulled high, if the control bits in this register are set as follows: – MUX_EN = 1b – INT_CON[2:0] = 111b – MUX_CFG[1:0] = 11b 0b = SPI SDO driven low. 1b = SPI SDO driven high.
5	MUX_OUT	R/W	0b	Control bit for diagnostic MUX output state test. The state of the DIAG_OUT pin is controlled by this bit if the control bits in this register are set as follows: – MUX_EN = 1b – MUX_CFG[1:0] = 00b 0b = The DIAG_OUT pin driven low. 1b = The DIAG_OUT pin driven high.
4-2	INT_CON[2:0]	R/W	0b	Control bits for device Interconnect test. The signal mux'd out to the DIAG_OUT pin is controlled by these bits if the control bits in this register are set as follows: – MUX_EN = 1b – MUX_CFG[1:0] = 11b 000b = No active interconnect test. 001b = MCU_ERR input. 010b = NCS input. 011b = SDI input. 100b = SCK input. 101b = Not applicable. 110b = Not applicable. 111b = SDO input controlled by the SPI_SDO bit.
1-0	MUX_CFG[1:0]	R/W	0b	Diagnostic MUX configuration. 00b = MUX output controlled by MUX_OUT bit. 01b = Digital MUX mode. 10b = Analog MUX mode. 11b = Device Interconnect mode (input pin interconnect test).

DIAG_MUX_SEL Register

DIAG_MUX_SEL is shown in and described in Figure 11-90 and described in Table 11-77.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Read (RD_DIAG_MUX_SEL)
Write (WR_DIAG_MUX_SEL)

Figure 11-90 Diagnostic Mux Select (DIAG_MUX_SEL) Register

7	6	5	4	3	2	1	0
MUX_SEL[7:0]
R/W-00000000b

Table 11-77 DIAG_MUX_SEL Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	DIAG_MUX_SEL[7:0]	R/W	00000000b	Diagnostic MUX channel select bits (see Section 11.9.9 for details). These bits become effective only when the INT_CON[2:0] bits are set to 000b.

WDT_WIN1_CFG Register

WDT_WIN1_CFG is shown in and described in Figure 11-91 and described in Table 11-78.

Return to Table 11-23

Initialization source: NPOR, RESET, WD_CFG change
Controller access: Read (RD_WDT_WIN1_CFG)
Write (WR_WDT_WIN1_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-91 Watchdog Window 1 Configuration (WDT_WIN1_CFG) Register

7	6	5	4	3	2	1	0
WD_RESP_WIN1_CFG[7:0] (WD_RW1C)
R/W-11111111b

Table 11-78 WDT_WIN1_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	WD_RESP_WIN1_CFG (WD_RW1C) WD_CLOSE_WIN_CFG (WD_CWC)	R/W	11111111b	Sets watchdog response window 1 (or close window) duration. t_{WD_RESP_WIN1} ( or t_{WD_CLOSE_WIN}) = (WD_RW1C[7:0] + 1) × 0.55 ms.

WDT_WIN2_CFG Register

WDT_WIN2_CFG is shown in and described in Figure 11-92 and described in Table 11-79.

Return to Table 11-23

Initialization source: NPOR, RESET, WD_CFG change
Controller access: Read (RD_WDT_WIN2_CFG)
Write (WR_WDT_WIN2_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.

Figure 11-92 Watchdog Window 2 Configuration (WDT_WIN2_CFG) Register

7	6	5	4	3	2	1	0
RESERVED			WD_RESP_WIN2_CFG[4:0] (WD_RW2C)
R-000b			R/W-11111b

Table 11-79 WDT_WIN2_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-5	RESERVED	R	000b	Reserved.
4-0	WD_RESP_WIN2_CFG (WD_RW2C) WD_OPEN_WIN_CFG (WD_OWC)	R/W	11111b	Sets watchdog response window 2 (or open window) duration. t_{WD_RESP_WIN2} (or t_{WD_OPEN_WIN}) = (WD_RW2C[4:0] + 1) × 0.55 ms.

WDT_Q&A_CFG Register

WDT_Q&A_CFG is shown in and described in Figure 11-93 and described in Table 11-80.

Return to Table 11-23

Initialization source: NPOR, RESET, LBIST run, WD_CFG change
Controller access: Read (RD_WDT_Q&A_CFG)
Write (WR_WDT_Q&A_CFG). Write access is only available in the DIAGNOSTIC state when the CFG_LOCK bit is set to 0b. Protected by the DEV_CFG_CRC.
Note: Confirm if this register must be initialized when device is in the RESET state.

Figure 11-93 Watchdog Q&A Configuration (WDT_Q&A_CFG) Register

7	6	5	4	3	2	1	0
WD_ANSW_GEN_CFG		WD_Q&A_POLY_CFG		WD_Q&A_SEED
R/W-00b		R/W-00b		R/W-1010b

Table 11-80 WDT_Q&A_CFG Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-6	WD_ANSW_GEN_CFG	R/W	0b	WD answer generation configuration.
5-4	WD_Q&A_POLY_CFG	R/W	0b	WD Q&A polynomial configuration.
3-0	WD_Q&A_SEED	R/W	1010b	WD Q&A LFSR polynomial seed value loaded when device is in the RESET state.

WDT_QUESTION_VALUE Register

WDT_QUESTION_VALUE is shown in and described in Figure 11-94 and described in Table 11-81.

Return to Table 11-23

Initialization source: NPOR, RESET, LBIST run, WD_CFG change
Controller access: Read-Only (RD_WDT_QUESTION_VALUE)

Figure 11-94 Watchdog Question Value (WDT_QUESTION_VALUE) Register

7	6	5	4	3	2	1	0
RESERVED				WD_QUESTION[3:0]
R-0000b				R-1100b

Table 11-81 WDT_QUESTION_VALUE Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-4	RESERVED	R	0000b	Reserved
3-0	WD_QUESTION[3:0]	R	1100b	Current watchdog question value. MCU must read (or calculate) the current watchdog question value to generate correct SPI responses.

WDT_STATUS Register

WDT_STATUS is shown in and described in Figure 11-95 and described in Table 11-82.

Return to Table 11-23

Initialization source: NPOR, RESET, LBIST run, WD_CFG change
Controller access: Read-Only (RD_WDT_STATUS)
Note: Refer to for details on initialization source for each bit.

Figure 11-95 Watchdog Status (WDT_STATUS) Register

7	6	5	4	3	2	1	0
WD_FC_ENDRV_DIS	WD_ANSW_CNT[1:0]		WD_CFG_CHG	ANSW_ERR	SEQ_ERR	TIME_OUT	ANSW_EARLY
RC-1b	R-11b		RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-82 WDT_STATUS Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	WD_FC_ENDRV_DIS	RC	1b	Error flag indicating WD_FAIL_CNT reaches or exceeds WD_FC_ENDRV_TH. NOTE: This flag bit is cleared on read access if WD_FAIL_CNT is below WD_FC_ENDRV_TH value. 0b = WD_FAIL_CNT ≥ WD_FC_ENDRV_TH 1b = WD_FAIL_CNT < WD_FC_ENDRV_TH
6-5	WD_ANSW_CNT[1:0]	R	11b	Current state of received watchdog answer counter. These status bits are updated with every received watchdog answer. NOTE: Initial state is 11b for WD_CFG = 0, and 01b for WD_CFG = 1. Initialization events for this bit is defined in Section 11.9.10.5.1.
4	WD_CFG_CHG	RC	0b	Watchdog configuration change status. 0b = No change in watchdog configuration. 1b = Change in watchdog configuration. Change in any of the followings constitutes watchdog configuration change: – The WDT_WIN1_CFG register – The WDT_WIN2_CFG register – The WDT_Q&A_CFG register – The WD_CFG bit
3	ANSW_ERR	RC	0b	Watchdog answer error flag. This flag bit is updated at the end of every watchdog cycle and initialized in the events defined in Section 11.9.10.5.1. 0b = All received WD_ANSWER_RESPx bytes were correct. 1b = Any of received WD_ANSWER_RESPx bytes was incorrect.
2	SEQ_ERR	RC	0b	Watchdog sequence error flag. This flag bit is updated at the end of every watchdog cycle and can be valid only for WD_CFG = 0. The bit is initialized in the events defined in Section 11.9.10.5.1. 0b = The number of received WD_ANSWER_RESP_x bytes in the response window 1 is equal to greater than 3. 1b = The number of received WD_ANSWER_RESP_x bytes in the response window 1 is less than 3.
1	TIME_OUT	RC	0b	Watchdog time-out error flag indicating no single watchdog answer is received within active watchdog cycle. This flag bit is updated at the end of every WD cycle. NOTE: This flag is useful to achieve synchronization between MCU and the watchdog module in TPS65313-Q1 either on transition from the RESET to the DIAGNOSTIC state, or after changing the watchdog configuration. In order to do so, MCU should not send WD response directly until this TIME_OUT flag is set. 0b = The number of WD_ANSWER_RESP_x bytes in the entire watchdog cycle is either 4 (WD_CFG = 0b), or 1 (WD_CFG = 1b). 1b = Less than 4 WD_ANSWER_RESP_x bytes were received in the entire watchdog cycle (WD_CFG = 0b), or no WD_ANSWER_RESPx byte was received (WD_CFG = 1b).
0	ANSW_EARLY	RC	0b	Watchdog early answer error flag indicating required number of answers were provided in the response window 1 or the Close window. This flag bit is updated at the end of every WD cycle. 0b = Less than 4 WD_ANSWER_RESP_x bytes were received in the response window 1 (WD_CFG = 0b), or no answer response was received in the Close window (WD_CFG = 1b). 1b = 4 WD_ANSWER_RESP_x bytes were received in the response window 1 (WD_CFG = 0b), or 1 answer response was received in the Close window (WD_CFG = 1b).

WDT_ANSWER Register

WDT_ANSWER is shown in and described in Figure 11-96 and described in Table 11-83.

Return to Table 11-23

Initialization source: NPOR, RESET
Controller access: Write (WR_WD_ANSWER)

Figure 11-96 Watchdog Answer (WDT_ANSWER) Register

7	6	5	4	3	2	1	0
WD_ANSWER[7:0]
W-N/A

Table 11-83 WDT_ANSWER Register Field Descriptions

Bit	Field	Type	Initial State	Description
7-0	WD_ANSWER[7:0]	W	N/A	MCU watchdog answer response byte. MCU must write the expected WD_ANSWER_RESPx byte into this register.

OFF_STATE_L_STAT Register

OFF_STATE_L_STAT is shown in and described in Figure 11-97 and described in Table 11-84.

Return to Table 11-23

Initialization source: NPOR, SPI RD Access
Controller access: Read-Only (RD_OFF_STATE_L_STAT)

Figure 11-97 OFF_STATE_L_STAT Register

7	6	5	4	3	2	1	0
START_UP_TO	DEV_EC_PWDN	VIN_OV	BUCKx_BOOST_VREG_FAIL	EE_CRC_ERR	RESET_TO	SYSCLK_ERR	POWER_ON_RST
RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b	RC-0b

Table 11-84 OFF_STATE_L_STAT Register Field Descriptions

Bit	Field	Type	Initial State	Description
7	START_UP_TO	RC	0b	Start-up time-out event caused device transition to the OFF state.
6	DEV_EC_PWDN	RC	0b	Device error count exceeding programmed device error count power-down threshold caused device transition to the OFF state.
5	VIN_OV	RC	0b	VIN overvoltage caused device transition to the OFF state. NOTE: Identical to VIN_OV bit in VMON_OV_STAT register.
4	BUCKx_BOOST_VREG_FAIL	RC	0b	BUCK1 or BUCK2 or BOOST or VREG Failure caused device transition to the OFF state. Read SAFETY_BUCK1_STAT, SAFETY_BUCK2_STAT, SAFETY_BOOST_STAT, VMON_UV and VMON_OV status registers to determine which BUCK1 and/or BUCK2 and/or BOOST and/or VREG failure occurred and forced device to the OFF state.
3	EE_CRC_ERR	RC	0b	EEPROM CRC error caused device transition to the OFF state.
2	RESET_TO	RC	0b	REST state time-out event caused device transition to the OFF state.
1	SYSCLK_ERR	RC	0b	Failure detection on SYSCLK by the analog clock monitor (ACLKMNT ) caused device transition to the OFF state.
0	POWER_ON_RST	RC	0b	Power-on reset (POR) event caused device transition to the OFF state.

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11.16.1.1.1 SPI Registers

DEV_REV Register

DEV_ID Register

DEV_STAT1 Register

DEV_STAT2 Register

DEV_CFG1 Register

DEV_CFG2 Register

DEV_CFG3 Register

DEV_CFG4 Register

SAFETY_CFG1 Register

SAFETY_CFG2 Register

SAFETY_CFG3 Register

SAFETY_CFG4 Register

SAFETY_CFG5 Register

SAFETY_CFG6 Register

SAFETY_CFG8 Register

EXT_VMON1_CFG Register

EXT_VMON2_CFG Register

PWR_CTRL Register

CLK_MON_CTRL Register

VMON_UV_STAT Register

VMON_OV_STAT Register

EXT_VMON_STAT Register

SAFETY_BUCK1_STAT1 Register

SAFETY_BUCK1_STAT2 Register

SAFETY_BUCK2_STAT1 Register

SAFETY_BUCK2_STAT2 Register

SAFETY_BOOST_STAT1 Register

SAFETY_BOOST_STAT2 Register

SAFETY_ERR_STAT1 Register

SAFETY_CLK_STAT Register

SAFETY_CLK_WARN_STAT Register

SAFETY_ABIST_ERR_STAT1 Register

SAFETY_ABIST_ERR_STAT2 Register

SAFETY_ABIST_ERR_STAT3 Register

SAFETY_ABIST_ERR_STAT4 Register

SAFETY_ABIST_ERR_STAT5 Register

SAFETY_ABIST_ERR_STAT6 Register

SAFETY_LBIST_ERR_STAT Register

SAFETY_ERR_STAT2 Register

SAFETY_ERR_STAT3 Register

SAFETY_ERR_STAT4 Register

SPI_TRANSFER_STAT Register

SAFETY_ABIST_CTRL Register

SAFETY_LBIST_CTRL Register

SAFETY_CHECK_CTRL Register

SAFETY_ERR_PWM_HMAX_CFG Register

SAFETY_ERR_PWM_HMIN_CFG Register

SAFETY_ERR_PWM_LMAX_CFG Register

SAFETY_ERR_PWM_LMIN_CFG Register

SAFETY_PWD_TH_CFG Register

SAFETY_DEV_CFG_CRC Register

DIAG_CTRL Register

DIAG_MUX_SEL Register

WDT_WIN1_CFG Register

WDT_WIN2_CFG Register

WDT_Q&A_CFG Register

WDT_QUESTION_VALUE Register

WDT_STATUS Register

WDT_ANSWER Register

OFF_STATE_L_STAT Register