JAJSIR5 データシート

JAJSIR5C October 2019 – October 2023 TPS65313-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RWG|40
- MPQF420

サーマルパッド・メカニカル・データ

発注情報

9.6 PLL/Oscillator and SYNC_IN Pin Characteristics

POS	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
2.0b	f_{PLL_UNLOCK}	Free-running PLL output clock frequency range as DC-DC converters switching frequency clock source		2.0	2.2	2.4	MHz
2.1	f_{PLL_LOCK}	PLL output clock frequency while synchronized to SYNC_IN input clock		2.0	2.2	2.4	MHz
2.2	D_f/f	Spread spectrum variation for internally generated and modulated around 2.2 MHz clock	Spread Spectrum type/mode for internally generated f_SW clock is set through EEPROM mapped bits	1.79	2.1	2.398	MHz
2.3	f_{SSM_STEP_INT_OSC}	Internal clock spread spectrum modulation steps	f_{SSM_STEP}/f_SW		1.25		%
2.4	f_{DITHER_STEP_SYNC}	SYNC_IN input clock dithering steps for 2.2 MHz of nominal frequency⁽¹⁾	f_{DITHER_STEP}/f_{SYNC_IN} =100 kHz / 2.2 MHz			5	%
2.5	f_{PLL_UNLOCK_ACC}	PLL Clock Output accuracy when VCO is in free-running mode.		-5		5	%
2.6	f_{PLL_LOCK_ACC}	PLL Clock Output accuracy when PLL is locked to SYNC_IN input clock		-1		1	%
2.7	t_{PLL_LOCK}	PLL Lock time⁽²⁾	When SYNC_IN clock frequency changes from 0 Hz to 2.2 MHz ±5%		100	150	µs
2.8	V_{SYNC_HIGH_THR}	SYNC_IN clock input high level threshold		1.84			V
2.9	V_{SYNC_LOW_THR}	SYNC_IN clock input low level threshold				0.76	V
2.10	D_SYNC	SYNC_IN clock input duty cycle		10		90	%
2.13	f_SYSCLK	System Clock Frequency		7.6	8	8.4	MHz
2.14	f_MODCLK	Internal Modulation Clock Frequency		2.09	2.2	2.31	MHz

(1) The input SYNC_IN clock can be modulated in a staircase (triangular) fashion step-by-step, with minimum step duration of 50 µs and clock frequency change of 50 kHz to 100 kHz.

(2) After the PLL is locked, SYNC_IN clock can change within ranges defined by f_{PLL_LOCK} with maximum frequency step defined by f_{DITHER_STEP_SYNC}.