If a SYNC_IN clock error is detected, the following occurs:

• The SYNC_CLK_ERR status bit is set in the SAFETY_CLK_STAT register.
• The device goes into the SAFE state.
• The PLL clock is disabled and the VCO clock is switched to free-running mode to provide an alternative clock source for the switched-mode regulators.
• The device error counter increments.
• The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.

If a PLL or VCO clock error is detected, the following occurs:

• The FSW_SRC_CLK_ERR status bit is set in the SAFETY_CLK_STAT register.
• The device goes into the SAFE state.
• The BUCK1 regulator, BUCK2 regulator, and BOOST converter are disabled without enabling resistive discharge.
• The device error counter increments.
• The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.
  Note:

  Eventually, as the BUCK1 regulator, BUCK2 regulator, and BOOST converter discharge to less than the respective UV-threshold level, a global RESET condition is met (as long as one regulator UV event is configured as a RESET state condition) and the device goes into the RESET state. When the device enters the RESET state, the BUCK1 regulator is enabled again (its default state) only if the SYNC_IN clock monitor and PLL (or VCO) clock monitor no longer indicates an error, the BUCK1 and BUCK2 regulators are discharged below the V_{BUCK1_RESTART_LEVEL} and V_{BUCK2_RESTART_LEVEL} voltage levels, and the BOOST converter is discharged below the V_{BOOST_RESTART_LEVEL} voltage levels. After the BUCK1 regulator is enabled, the BUCK2 regulator and the BOOST converter are enabled after the BUCK1 output exceeds its UV-threshold level.

  All the BUCK1 monitoring and protection mechanisms are active, and if any critical conditions are still present, the BUCK1 regulator is disabled again. If the BUCK1 regulator never recovers while in the RESET state, the RESET state time-out event places the device into the OFF state.

As the rails discharge to less than their UV-threshold levels, the device enters the RESET state. While in the RESET state, the SYNC_IN clock monitor is disabled, PLL synchronization to the SYNC_IN input clock is stopped, and the PLL starts a gradual transition to the free-running VCO clock. The switched-mode regulators are enabled by internal start-up circuit only when neither the PLL (or VCO) clock monitor (DIG_CLK_MON6) nor the respective clock monitors (DIG_CLK_MON3 – DIG_CLK_MON5) for the switched-mode regulators detect any errors.

In the RESET state, the SYNC_IN clock monitor is disabled (the DIG_SYNC_CLK_MON_EN control bit is cleared) because the MCU stops driving the clock when rebooting. The regulators are enabled as soon as the PLL (or VCO) clock monitor reports that the clock is in good condition. The SYNC_IN clock monitor stays disabled until the MCU gets out of reset and completes re-boot (after NRES rising edge and the device goes into the DIAGNOSTIC state). After reboot the MCU sends a SPI command to enable the SYNC_IN clock monitor (to set the DIG_SYNC_CLK_MON_EN control bit). The MCU should enable the SYNC_IN clock monitor only after it has started to drive the SYNC_IN clock input.

If the failure is because of the PLL (or VCO) clock failure, the device stays in the RESET state until the PLL (or VCO) clock recovers. If the PLL (or VCO) clock does not recover, the RESET state time-out event occurs and the device goes into the OFF state and latches the RESET state time-out event in the Analog_Latch.