Table 11-17 shows the response
frame format of the SPI data status during a command or a read or write access.
Table 11-17 Response Frame Format of the Device SPI Data—Command or Read or Write Access
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| STAT[7] |
STAT[6] |
STAT[5] |
STAT[4] |
STAT[3] |
STAT[2] |
STAT[1] |
STAT[0] |
STAT[7:5]
These status bits are in a fixed toggling pattern (101) for protection against short-to-ground or short-to-supply-voltage conditions.
STAT[4]
This status bit indicates that device is in the SAFE state.
STAT[3]
This status bit indicates a software (SW) Interrupt event when one or more status bits are set in the SAFETY_ERR_STATx, SAFETY_CLK_STAT, SAFETY_CLK_WARN_STAT, or SAFETY_ABIST_ERR_STATx registers. This bit stays set until all error
status bits are cleared by reading the listed status registers.
STAT[2]
This status bit indicates that the watchdog has detected a WD Q&A sequence run error, (indicated by the ANSW_ERR status bit), a sequence error (indicated by SEQ_ERR status bit), or a WD Q&A sequence run time-out event. The
SPI sets this bit only in the first SPI-frame after the watchdog has detected such a failure. In the next SPI-frame after that, the SPI clears this bit.
The SPI clears this bit when the device goes into
the RESET state.
Note: A write access to the WDT_WIN1_CFG or WDT_WIN2_CFG register does not set the STAT[2] status bit.
STAT[1]
This status bit indicates that the ESM has detected an incorrect event (indicated by MCU_ESM_FAIL status bit which increments the MCU_ESM_FC[3:0] counter). The SPI sets this bit only in the fist SPI frame after the ESM detects the
incorrect event. In the next SPI frame after that, the SPI clears this bit.
The SPI clears this bit when the device goes into the RESET state.
STAT[0]
This status bit indicates that the previous SPI frame was invalid. This bit clears when the next SPI frame transmission is valid or when the device goes to the RESET state. This bit is set only when one of events latched in the
SPI_TRANSFER_STAT register are detected during the previous SPI frame. The STAT[0] status bit indicates different invalid SPI transfer events that are latched in the SPI_INV_TRAN_STAT register. The events are as follows:
- A SPI SDO error (mismatch between the SPI driver output and SDO pin feedback input).
- A SPI frame shorter than 24 or 16 SPI-clock cycles (or prematurely terminated SPI frame).
- A SPI
frame longer than 24 or 16 SPI-clock cycles.
- An invalid SPI command (essentially a command reserved for production test).
- An undefined SPI command (essentially an unassigned
command).
- Master CRC error on the received SPI frame.
- A logic-high level on the SCK pin at the moment the logic level on the NCS pin changes from high to low.
- A logic-high level
on the SCK pin at the moment the logic level on the NCS pin changes from low to high.
- A SPI transfer terminated by a RESET event.
The SPI frame, or command, is ignored
each time when one of the error conditions, condition 2 through condition 7, is
detected. A SPI SDO error does not cause the device to ignore a valid SPI command
received from the MCU SPI master device.