JAJSIR5C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 デバイスの機能ブロック図
  6. 5 Revision History
  7. 6 概要 (続き)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.9.2 Supply Voltage Monitor (VMON)

The supply voltage monitor (VMON) monitors the device supply voltage, all regulator output voltages, the internal regulators, and up to two external supply rails. The SPI register has VMON status bits (UV, OV, and OVP) to indicate an undervoltage or overvoltage event (error event) for each monitored voltage rail. The device keeps the VMON status bits set to 0b during the ramp up of the monitored rails. The device sets the status bit to 1b when the monitored rail is outside the specified range. The status bit stays set until it is cleared by a valid SPI read command if the corresponding fault condition is removed.

The complete VMON block is supplied by a separate supply pin (VIN_SAFE). The reference voltages for the VMON module (VREF_MON) are derived from a redundant band-gap reference (BG2) which is independent of the primary band-gap reference (BG1). BG1 provides reference voltages (VREF_REG) for the regulators and other functional blocks. The VMON module has a deglitch timer for each monitored supply rail. If the error event occurs for a time period shorter than the deglitch time, the VMON module does not set the corresponding VMON status bit. The device keeps the VMON status bits set to 0b during the ramp up of the monitored voltage rails to make sure monitoring is reliable without false setting of the VMON status bits. When the device is in the operating states, the voltage monitoring is continuous and stays active even after the respective regulator has been disabled.

The analog-built-in self-test (ABIST) runs the VMON modules' diagnostic check. The ABIST is executed during device power-up or when activated by the system MCU when the device is in the DIAGNOSTIC, ACTIVE, or SAFE state. Each monitored voltage rail is emulated for an undervoltage, overvoltage, and overvoltage protection condition on the corresponding comparator inputs which forces the corresponding comparator to toggle multiple times. The comparator output toggling pattern is observed and checked by the ABIST digital controller. The monitored voltage rails are not affected during the ABIST. No undervoltage or overvoltage events occur on any of monitored rails because of these diagnostic tests.

Table 11-1 provides an overview of the voltage monitoring.

Table 11-1 Voltage Monitoring Overview
VOLTAGE RAIL MONITORED PIN DETECTION THRESHOLD RANGE DEGLITCH TIME DEVICE BEHAVIOR UPON DETECTION (SPI FLAG, STATE TRANSITION, NRES/ENDRV PIN STATUS) ABIST
UV OV OVP UV/OV OVP UV OV OVP
VBAT AVIN 5.8 V to 6.6 V(1) 36 V to 40 V — UV: 90 µs to 110 µs
OV: 10 µs to 20 µs		 — VMON_UV_STAT[6]
No change in state
No change in NRES, ENDRV/nIRQ = 0 if VIN_BAD_IRQ_EN = 1(2)		 VMON_OV_STAT[6]
OFF state
NRES = 0, ENDRV/nIRQ = 0		 — NO
VBUCK1(3) VSENSE1 –5.0% to –2.5% 2.5% to 5.0% 6% to 10% 21 µs to 39 µs 21 µs to 39 µs VMON_UV_STAT[0]
RESET state if BUCK1_UV_RST_EN = 1,
SAFE state if BUCK1_UV_RST_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BUCK1_UV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if BUCK1_UV_RST_EN = 0		 VMON_OV_STAT[0]
RESET state if BUCK1_OV_RST_EN = 1,
SAFE state if BUCK1_OV_RST_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BUCK1_OV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if BUCK1_OV_RST_EN = 0		 SAFETY_BUCK1_STAT1[3]
OFF state if BUCK1_OVP_OFF_EN = 1,
SAFE state if BUCK1_OVP_OFF_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BUCK1_OVP_OFF_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if BUCK1_OVP_OFF_EN = 0		 YES
VBUCK2 VSENSE2 –5.0% to –2.5% 2.5% to 5.0% 6% to 10% 21 µs to 39 µs 21 µs to 39 µs VMON_UV_STAT[1]
RESET state if BUCK2_UV_RST_EN = 1,
No state change if BUCK2_UV_RST_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BUCK2_UV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if BUCK2_UV_RST_EN = 0		 VMON_OV_STAT[1]
RESET state if BUCK2_OV_RST_EN = 1,
SAFE state if BUCK2_OV_RST_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BUCK1_OV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if BUCK2_OV_RST_EN = 0		 SAFETY_BUCK2_STAT1[3]
SAFE state(4)
NRES = 1, ENDRV/nIRQ = 0 		YES
VBOOST VSENSE3 –5.0% to –2.5% 2.5% to 5.0% 6% to 10% 21 µs to 39 µs 21 µs to 39 µs VMON_UV_STAT[3]
RESET state if BOOST_UV_RST_EN = 1,
No change in state if BOOST_UV_RST_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BOOST_UV_RST_EN = 1,
No change in NRES or ENDRV/nIRQ if BOOST_UV_RST_EN = 0		 VMON_OV_STAT[3]
RESET state if BOOST_OV_RST_EN = 1,
SAFE state if BOOST_OV_RST_EN = 0
NRES = 0, ENDRV/nIRQ = 0 if BOOST_OV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if BOOST_OV_RST_EN = 0		 SAFETY_BOOST_STAT1[3]
SAFE state(5)
NRES = 1, ENDRV/nIRQ = 0 		YES
EXT_VSENSEx EXT_VSENSEx –4.8% to –3.0% 3.0% to 4.8% — 21 µs to 39 µs — EXT_VMON_STAT[1:0]
RESET state if EXT_VMONx_UV_RST_EN = 1,
SAFE state if EXT_VMONx_UV_RST_EN = 0 AND EXT_VMONx_UV_IRQ_EN = 1
NRES = 0, ENDRV/nIRQ = 0 if EXT_VMONx_UV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if EXT_VMONx_UV_RST_EN = 0 AND EXT_VMONx_UV_IRQ_EN = 1		 EXT_VMON_STAT[5:4]
RESET state if EXT_VMONx_OV_RST_EN = 1,
SAFE state if EXT_VMONx_OV_RST_EN = 0 AND EXT_VMONx_OV_IRQ_EN = 1
NRES = 0, ENDRV/nIRQ = 0 if EXT_VMONx_OV_RST_EN = 1,
NRES = 1, ENDRV/nIRQ = 0 if EXT_VMONx_OV_RST_EN = 0 AND EXT_VMONx_OV_IRQ_EN = 1		 — YES
VREG VREG 3.7 V to 3.9 V 5.9 V to 6.5 V — UV: 24 µs to 40 µs OV: 10 µs to 20 µs — VMON_UV_STAT[4]
OFF state
NRES = 0, ENDRV/nIRQ = 0		 VMON_OV_STAT[4]
OFF state
NRES = 0, ENDRV/nIRQ = 0		 — YES
VIO VIO — 5.9 V to 6.5 V — 10 µs to 20 µs — — VMON_OV_STAT[7]
No change in state
NRES and ENDRV/nIRQ HiZ as VIO gets disconnected(6)		 — NO
(1) VIN bad falling threshold; VIN_BAD_TH[1:0] bit is set to 0b.
(2) No change in the ENDRV/nIRQ output if the VIN_BAD_IRQ_EN bit is set to 0b.
(3) The BUCK1 EOVP results in a transition to the OFF state.
(4) If the BUCK2 OVP event is still present for the tBUCK2_OVP_OFF duration after the BUCK2 regulator is disabled, then the TPS65313-Q1 device goes into the OFF state.
(5) If the BOOST OVP event is still present for the tBOOST_OVP_OFF duration after the BOOST converter is disabled, then the TPS65313-Q1 device goes into the OFF state.
(6) The pins can still be pulled down if that is the intended status, but the pins cannot be pulled up as the pin drivers get disconnected from their supply, VIO.