JAJSIR5C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 デバイスの機能ブロック図
  6. 5 Revision History
  7. 6 概要 (続き)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.11 Voltage Monitors for Regulators Characteristics

VIN/AVIN/VIN_SAFE = 4 V to 36 V, TA = -40°C to 125°C, TJ up to 150°C, unless otherwise noted.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
7.0 VREF_MON Voltage reference for monitoring circuits derived from BG2 VBG2 = 1.2V (TYP) 1.0 V
7.0a VREF_REG Voltage reference for regulator circuits derived from BG1 VBG1 = 1.2V (TYP) 1.2 V
7.1 VREF_MON_ACC Voltage reference accuracy for monitoring circuits -1 +1 %
7.1a VREF_REG_ACC Voltage reference accuracy for regulator circuits -1 +1 %
7.2a tSMPS_UV_OV_OVP Deglitch time between Under-Voltage/Over-Voltage/Over-Voltage-Protection event to NRES output low Measured from the start of Wide-VIN BUCK1/LV BUCK2/BOOST UV, OV, or OVP event to the NRES pin falling edge as the TPS65313B-Q1 transitions to either the RESET state or OFF state. It takes up to 5 system clock cycles from detected valid UV/OV/OVP event until device transitions to RESET state or OFF state. 21 30 39 µs
7.2b tSMPS_UV_OV_OVP Deglitch time between Under-Voltage/Over-Voltage/Over-Voltage-Protection event to ENDRV/nIRQ output low Measured from Wide-VIN BUCK1/LV BUCK2/BOOST UV, OV, or OVP event to the ENDRV/nIRQ pin falling edge as the TPS65313B-Q1 transitions to the SAFE state.  It takes up to 5 system clock cycles from detected valid UV/OV/OVP event until device transitions to SAFE state. 21 30 39 µs
7.2c tVREG_UV Deglitch time from Under-Voltage event to NRES output low Measured from the start of VREG UV event to the NRES pin falling edge as the TPS65313B-Q1 transitions to the OFF state.  It takes up to 5 system clock cycles from detected valid UV event until device transitions to OFF state and drives NRES low. 24 32 40 µs
7.2d tVREG_OV Deglitch time between Over-Voltage event to NRES output low Measured from the start of VREG OV event to the NRES pin falling edge as the TPS65313B-Q1 transitions to the OFF state.  It takes up to 5 system clock cycles from detected valid OV event until device transitions to OFF state and drives NRES low. 10 15 20 µs
7.2e tVIO_OV VIO Over-Voltage deglitch time  Measured from the start of VIO OV event to the VIO_OV status bit is set. 10 15 20 µs
7.5a tBUCK2_OVP_OFF Deglitch time for disabling Wide-VIN BUCK1 if LV BUCK2 Over-Voltage-Protection event is detected after LV BUCK2 is disabled due to prior LV BUCK2 Over-Voltage-Protection event detection
 Measured from the start of LV BUCK2 OVP event to the NRES pin falling edge as the TPS65313B-Q1 transitions to the OFF state.  It takes up to 5 system clock cycles from detected valid OVP event until device transitions to OFF state and drives NRES low. 21 30 39 µs
7.5b tBOOST_OVP_OFF Deglitch time for disabling Wide-VIN BUCK1 if BOOST Over-Voltage-Protection event is detected after BOOST is disabled due to prior BOOST Over-Voltage-Protection event detection.
 Measured from the start of BOOST OVP event to the NRES pin falling edge as the TPS65313B-Q1 transitions to the OFF state.  It takes up to 5 system clock cycles from detected valid OVP event until device transitions to OFF state and drives NRES low. 60 76 90 µs
7.6 VIO_OV VIO Over-Voltage threshold
 5.9 6.5 V
7.7 VBUCK1_UV Wide-VIN BUCK1 Under-Voltage detection threshold, expressed in percentage from VBUCK1 nominal voltage. VSENSE1 falling -5.0 -2.5 %
7.8 VBUCK1_OV Wide-VIN BUCK1 Over-Voltage detection threshold, expressed in percentage from VBUCK1 nominal voltage. VSENSE1 rising 2.5 5.0 %
7.9 VBUCK1_OVP Wide-VIN BUCK1 Over-Voltage Protection threshold, expressed in percentage from VBUCK1 nominal voltage. VSENSE1 rising 6 10 %
7.9b VBUCK1_EOVP Wide-VIN BUCK1 Extreme Over-Voltage Protection threshold VSENSE1 rising 3.84 4 4.1610 V
7.10 VBUCK2_UV LV BUCK2 Under-Voltage detection threshold, expressed in percentage from VBUCK2 nominal voltage.
 VSENSE2 falling -5.0 -2.5 %
7.11 VBUCK2_OV LV BUCK2 Over-Voltage detection threshold, expressed in percentage from VBUCK2 nominal voltage.
 VSENSE2 rising 2.5 5.0 %
7.12 VBUCK2_OVP LV BUCK2 Over-Voltage Protection threshold, expressed in percentage from VBUCK2 nominal voltage. VSENSE2 rising 6 10 %
7.13 VBOOST_UV LV BOOST Under-Voltage detection threshold, expressed in percentage from VBOOST nominal voltage. VSENSE3 falling -5.0 -2.5 %
7.14 VBOOST_OV LV BOOST Over-Voltage detection threshold, expressed in percentage from VBOOST nominal voltage. VSENSE3 rising 2.5 5.0 %
7.15 VBOOST_OVP LV BOOST Over-Voltage Protection threshold, expressed in percentage from VBOOST nominal voltage. VSENSE3 rising 6 10 %
7.18 VREG_UV VREG under-voltage detection threshold VREG falling 3.7 3.9 V
7.19 VREG_OV VREG over-voltage threshold VREG rising 5.9 6.5 V
7.26a fSYSCLK_ACKMNT_SLOW Analog System Clock Monitor slow clock error detection threshold before EEPROM download 455 700 945 kHz
7.26b fSYSCLK_ACKMNT_SLOW Analog System Clock Monitor slow clock error detection threshold after EEPROM download 4.75 5.60 6.45 MHz
7.27a fSYSCLK_ACKMNT_FAST Analog System Clock Monitor fast clock error detection threshold before EEPROM download 3.38 5.20 7.02 MHz
7.27b fSYSCLK_ACKMNT_FAST Analog System Clock Monitor fast clock error detection threshold after EEPROM download 8.84 10.40 11.96 MHz
7.31 fPLL_SMPS_DCKMNT_SLOW_ERR Digital PLL/SMPS Clock Monitor slow clock error detection threshold 1.58 1.66 1.75 MHz
7.33 fPLL_SMPS_DCKMNT_FAST_ERR Digital PLL/SMPS Clock Monitor fast clock error detection threshold 2.40 2.53 2.67 MHz