JAJSIR5C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 デバイスの機能ブロック図
  6. 5 Revision History
  7. 6 概要 (続き)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.9.4.4 ABIST Scheduler in the ACTIVE State

The system MCU can activate the ABIST scheduler in the ACTIVE state through the ABIST_GROUPx_START control bits in the SAFETY_ABIST_CTRL register when the ABIST_SCHED_EN configuration bit in the SAFETY_CFG2 register is set. When enabled, the scheduler runs continuously until it is commanded to stop by clearing the ABIST_GROUP_xSTART control bits or when the device goes from the ACTIVE state. The ABIST scheduler cannot run in the DIAGNOSTIC and SAFE state (setting the ABIST_SCHED_EN configuration bit has no impact on ABIST runs in the DIAGNOSTIC and SAFE states when the ABIST_GROUPx_START control bits are set).

At any time when an ABIST group of tests is set to run, the ABIST tests are activated only during the analog comparator output steady state (sampled analog comparator output matches respective deglitched output and SPI status bit).

If none of the previously listed conditions are met, initiation of an ABIST run will be delayed. The maximum wait time to start an ABIST is time limited by its ABIST time-out function.

If any of the scheduled diagnostic tests fail during an ABIST run when the device is in the ACTIVE state or an ABIST start time-out event occurs, the device response depends on the ABIST_ACTIVE_FAIL_RESP configuration bit setting in the SAFETY_CFG2 register.

If the ABIST_ACTIVE_FAIL_RESP bit is set to 0b, the following occurs:

  • The device goes into the SAFE state.
  • One or more (out of seven) of the ABIST error status bits in the SAFETY_ABIST_ERR_STAT1 through the SAFETY_ABIST_ERR_STAT4 registers are set.
  • The ENDRV/nIRQ pin is asserted low to interrupt the external system MCU.

If the ABIST_ACTIVE_FAIL_RESP bit is set to 1b, the following occurs:

  • The device stays in the SAFE state.
  • One or more (out of seven) of the ABIST error status bits in the SAFETY_ABIST_ERR_STAT1 through SAFETY_ABIST_ERR_STAT4 registers are set.
  • The SW interrupt bits are asserted in the SPI status word for each SPI access until the respective ABIST fail status bits are cleared by reading the SAFETY_ABIST_ERR_STATx status registers.

An ABIST-start time-out event can indicate a deglitch function failure, which can be detected by observing the GROUPx_ERR bit being set, but none of the individual status bits in the
SAFETY_ABIST_ERR_STATx registers are set. A deglitch function failure can be detected by the LBIST as well. Before a scheduled ABIST run, two cases of analog comparator failures can occur. These cases are defined as follows:

    Case 1 An analog comparator fails in such a way that always indicates an active condition (for an example, driving HIGH and signaling all the time that an OV event occurred).

    After the deglitch time, the analog comparator output propagates through the deglitch function and is latched in a SPI-mapped register bit.

    The ABIST start condition is met (the analog comparator output is equal to the deglitch function output) and the ABIST run starts.

    Because the analog comparator is stuck HIGH (for an example, driving HIGH all the time even when a monitored voltage is in the nominal range) the ABIST run detects an analog comparator failure and signals an ABIST run fail.
    Case 2 An analog comparator fails in such a way that the LBIST cannot detect an active condition (for an example, driving LOW all the time and unable to detect a valid OV event).

    The ABIST start condition is met (the analog comparator output is equal to the deglitch function output) and the ABIST run starts.

    Because the analog comparator is stuck LOW (for an example, driving LOW all the time even when a monitored voltage is in the OV range) the ABIST run detects an analog comparator failure and signals an ABIST run fail.

Undervoltage and overvoltage comparator diagnostic tests do not impact the regulated output-voltage rails. This ABIST run does not check the current limit circuit of the regulators and the circuits of the VREG UV, VREG OV, VIN UV, and VIN OV voltage monitors. When the VREG regulator is enabled, running the VREG UV and VREG OV diagnostics causes the VREG output to become uncontrollable and for that reason not included in this ABIST run.

Figure 11-11 shows an example with tests for all four ABIST groups when the ABIST_GROUP1_START, ABIST_GROUP2_START, ABIST_GROPU_START3, and ABIST_GROUP_START4 control bits are set.

GUID-8F19988A-33B2-4D7E-8452-E6DDAE6BABF9-low.gif
  1. ENDRV toggling is checked by the system MCU.
Figure 11-11 The ABIST Scheduler in the ACTIVE State

Figure 11-12 shows an example with tests for two ABIST groups when only the ABIST_GROUP1_START and ABIST_GROUP3_START control bits are set.

GUID-D0BC89B0-8E37-4753-AF00-1B2EAB141D9B-low.gif Figure 11-12 ABIST Scheduler in the ACTIVE State

The ABIST scheduler runs the activated ABIST group of tests periodically in the ACTIVE state when at least one of the ABIST_GROUPx_START bits is set and while the ABIST_SCHED_EN configuration bit is set. The test repetition period is programmable through the ABIST_SCHED_DLY configuration bits in the SAFETY_CFG8 register. This time period is defined by Figure 11-10. The time delay between any two ABIST groups of tests can be from 281.6 ms to 10380.9 s.

GUID-60771FBD-C397-4C29-8FE6-24F6BF25AADA-low.gif Figure 11-13 ABIST Scheduler

In the ACTIVE state, the t2 time interval is defined by Equation 1

Equation 1. t2 = (ABIST_SCHED_DLY + 1) × 256 × (tWD_WIN1 + tWD_WIN2)

where

  • ABIST_SCHED_DLY is set by the configuration bits in the SAFETY_CFG8 register.
  • tWD_WIN1 is a Watchdog Window #1 duration set by the configuration bits in the WDT_WIN1_CFG register.
  • tWD_WIN2 is a Watchdog Window #2 duration set by the configuration bits in the WDT_WIN2_CFG register.