JAJSIR5C October 2019 – October 2023 TPS65313-Q1
PRODUCTION DATA
The analog wake-up detection circuit monitors the WAKE pin when the device is in the OFF state. With a valid power supply at the supply input pins (VIN, AVIN, and VIN_SAFE), this circuit is the only active circuit in the device when the device is in the OFF state, reducing device power consumption.
When the WAKE pin is driven high, the device deglitches the input wake-up signal using a low-power oscillator clock for approximately 130 µs and latches the signal in the analog wake-up latch (indicated as a WAKE_L bit). When the WAKE_L bit is set, the wake-up latch is cleared only by the device NPOR event, a SPI command (CLR_WAKE_LATCH), or failure conditions that force the device to go to the OFF state (fault events 2 through 17). The wake-up latch is also cleared anytime when the device goes into the OFF state.
The wake-up latch is cleared as the device starts to go to the OFF state. The internal signal that clears the wake-up latch remains active (keep clearing the power wake-up latch) until the device goes to the OFF state. This prevents the wake-up latch from getting set again and triggers a new power-up before the device goes into the OFF state.
In addition to the power wake-up latch, the analog wake-up latch includes additional analog latches (Analog_Latch) to retain failure conditions that force the device to go to the OFF state. The list of latches includes the following:
In case the BUCK2 overvoltage condition is still detected 28 µs to 30 µs after the BUCK2 regulator is disabled, the device goes to the OFF state and the BUCK2_OVP status bit is latched in the Analog_Latch.
In case the BOOST overvoltage condition is still detected 72 µs to 80 µs after the BOOST converter is disabled, the device goes to the OFF state and the BOOST OVP status bit is latched in the Analog_Latch.
These status latches are set in the analog power domain of the TPS65313-Q1 device as the device goes into the OFF state. These latches are cleared only if the device loses battery supply at the AVIN pin or when the device wakes up and exits the OFF state after a valid WAKE input event. As the device starts up after a valid WAKE input event, the content of the analog status latches are copied to the OFF_STATE_L_STAT and the corresponding BUCK1, VMON, and SAFETY status registers after an internal NPOR is asserted high and the EEPROM has been downloaded. Then the analog status latches are cleared.
| NUMBER | OFF STATE CONDITION | OFF_STATE_L REGISTER BIT | CORRESPONDING STATUS REGISTER BIT |
|---|---|---|---|
| 1. | Power-on reset | POWER_ON_RST | |
| 2. | Analog or digital system clock-monitor error | SYSCLK_ERR | ANA_SYSCLK_ERR bit and DIG_SYSCLK_ERR bit in SAFETY_CLK_STAT register |
| 3. | RESET state time-out | RESET_TO | |
| 4. | EEPROM CRC error | EE_CRC_ERR | EE_CRC_ERR bit in SAFETY_ERR_STAT1 register |
| 5. | BUCK1 overtemperature | BUCKx_BOOST_VREG_FAIL | BUCK1_OT_STD bit in SAFETY_BUCK1_STAT1 register |
| 6. | BUCK1 short-circuit to GND | BUCKx_BOOST_VREG_FAIL | BUCK1_SCG bit in SAFETY_BUCK1_STAT1 register |
| 7. | BUCK1 overvoltage protection | BUCKx_BOOST_VREG_FAIL | BUCK1_OVP bit in SAFETY_BUCK1_STAT1 register |
| 8. | BUCK1 low-side sink overcurrent | BUCKx_BOOST_VREG_FAIL | BUCK1_LS_SINK_OVC bit in SAFETY_BUCK1_STAT1 register |
| 9. | BUCK1 extreme overvoltage protection | BUCKx_BOOST_VREG_FAIL | BUCK1_EOVP bit in SAFETY_BUCK1_STAT1 register |
| 10. | BUCK1 power GND loss | BUCKx_BOOST_VREG_FAIL | BUCK1_PGND_LOSS bit in SAFETY_BUCK1_STAT1 register |
| 11. | BUCK2 overvoltage protection | BUCKx_BOOST_VREG_FAIL | BUCK2_OVP bit in SAFETY_BUCK2_STAT1 register |
| 12. | BOOST overvoltage protection | BUCKx_BOOST_VREG_FAIL | BOOST_OVP bit in SAFETY_BOOST_STAT1 register |
| 13. | VREG undervoltage | BUCKx_BOOST_VREG_FAIL | VREG_UV bit in VMON_UV_STAT register |
| 14. | VREG overvoltage | BUCKx_BOOST_VREG_FAIL | VREG_OV bit in VMON_OV_STAT register |
| 15. | VIN overvoltage | VIN_OV | VIN_OV bit in VMON_OV_STAT register |
| 16. | Device error-counter power down | DEV_EC_PDWN | |
| 17. | Start-up time-out | START_UP_TO |
If a power-up time-out failure that puts the device in the OFF state is followed by a new power-up event (because the WAKE pin is driven above its VWAKE-ON threshold level), the number of analog-latched bits could be more than the START_UP_TO bit. The reason for this increased number of latched bits is because the previous OFF state transition condition could be caused by any of the previously listed OFF-state failure conditions.
The AUTO_START_DIS configuration bit is latched in the analog wake-up latch as well as in the DEV_STAT1 register. This bit is initialized to 0b at a NPOR event, only when an NPOR event is preceded by loss of battery supply at the VIN, VINA, and VIN_SAFE pins. The AUTO_START_DIS bit can be set to 1b by the SET_AUTO_START_DIS command with data 0xAA, or when a valid VREG OV event is detected. This bit can be cleared by the CLR_AUTO_START_DIS command with data 0x55. This bit controls whether the device's auto-restart is allowed, when the device goes to the OFF state, and while the WAKE input pin is still driven above its VWAKE-ON threshold level.
When the device is in the INIT state during power-up, the device NPOR stays asserted if the system-clock error, VIN overvoltage, or both are detected. The NPOR is asserted until the INIT state time-out event puts the device to the OFF state, and the START_UP_TO bit is latched in the Analog_Latch (the SYSCLK_ERR and VIN_OV bits are not latched in the Analog_Latch).
When the device starts and the NPOR for the digital core is released, the device goes into the OFF state with respective status bits latched in the Analog_Latch, if the SYSCLK failure, VIN supply overvoltage, or both are detected.