SLVSCQ2 July   2015 TPS65400-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Operational Parameters
    8. 7.8 Package Dissipation Ratings
    9. 7.9 Typical Characteristics: System Efficiency
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Startup Timing and Power Sequencing
        1. 8.3.1.1 Startup Timing
        2. 8.3.1.2 External Sequencing
        3. 8.3.1.3 Internal Sequencing
      2. 8.3.2  UVLO and Precision Enables
      3. 8.3.3  Soft-Start and Prebiased Startup
        1. 8.3.3.1 Analog Soft-Start (Default) and Digital Soft-Start
        2. 8.3.3.2 Soft-Start Capacitor Selection
      4. 8.3.4  PWM Switching Frequency Selection
      5. 8.3.5  Clock Synchronization
      6. 8.3.6  Phase Interleaving
      7. 8.3.7  Fault Handling
      8. 8.3.8  OCP for SW1 to SW4
      9. 8.3.9  Overcurrent Protection for SW1 to SW4 in Current Sharing Operation
      10. 8.3.10 Recovery on Power Loss
      11. 8.3.11 Feedback Compensation
      12. 8.3.12 Adjusting Output Voltage
      13. 8.3.13 Digital Interface - PMBus
      14. 8.3.14 Initial Configuration
    4. 8.4 Device Functional Modes
      1. 8.4.1 CCM Operation Mode
      2. 8.4.2 CCM/DCM Operation Mode
      3. 8.4.3 Current Sharing Mode
    5. 8.5 Register Maps
      1. 8.5.1 PMBus
        1. 8.5.1.1 Overview
        2. 8.5.1.2 PMBus Protocol
          1. 8.5.1.2.1  PMBus Protocol
          2. 8.5.1.2.2  Transactions (No PEC)
          3. 8.5.1.2.3  Addressing
          4. 8.5.1.2.4  Startup
          5. 8.5.1.2.5  Bus Speed
          6. 8.5.1.2.6  I2CALERT Terminal
          7. 8.5.1.2.7  CONTROL Terminal
          8. 8.5.1.2.8  Packet Error Checking
          9. 8.5.1.2.9  Group Commands
          10. 8.5.1.2.10 Unsupported Features
      2. 8.5.2 PMBus Register Descriptions
        1. 8.5.2.1 Overview
        2. 8.5.2.2 Memory Model
        3. 8.5.2.3 Data Formats
        4. 8.5.2.4 Fault Monitoring
      3. 8.5.3 PMBus Core Commands
        1. 8.5.3.1  (00h) PAGE
        2. 8.5.3.2  (01h) OPERATION
        3. 8.5.3.3  (03h) CLEAR_FAULTS
        4. 8.5.3.4  (10h) WRITE_PROTECT
        5. 8.5.3.5  (11h) STORE_DEFAULT_ALL
        6. 8.5.3.6  (19h) CAPABILITY
        7. 8.5.3.7  (78h) STATUS_BYTE
        8. 8.5.3.8  (79h) STATUS_WORD
        9. 8.5.3.9  (7Ah) STATUS_VOUT
        10. 8.5.3.10 (80h) STATUS_MFR_SPECIFIC
        11. 8.5.3.11 (98h) PMBUS_REVISION
        12. 8.5.3.12 (ADh) IC_DEVICE_ID
        13. 8.5.3.13 (AEh) IC_DEVICE_REV
      4. 8.5.4 Manufacturer-Specific Commands
        1. 8.5.4.1  (D0h) USER_DATA_BYTE_00
        2. 8.5.4.2  (D1h) USER_DATA_BYTE_01
        3. 8.5.4.3  (D2h) PIN_CONFIG_00
        4. 8.5.4.4  (D3h) PIN_CONFIG_01
        5. 8.5.4.5  (D4h) SEQUENCE_CONFIG
        6. 8.5.4.6  (D5h) SEQUENCE_ORDER
        7. 8.5.4.7  (D6h) IOUT_MODE
        8. 8.5.4.8  (D7h) FREQUENCY_PHASE
        9. 8.5.4.9  (D8h) VREF_COMMAND
        10. 8.5.4.10 (D9h) IOUT_MAX
        11. 8.5.4.11 (DAh) USER_RAM_00
        12. 8.5.4.12 (DBh) SOFT_RESET
        13. 8.5.4.13 (DCh) RESET_DELAY
        14. 8.5.4.14 (DDh) TON_TOFF_DELAY
        15. 8.5.4.15 (DEh) TON_TRANSITION_RATE
        16. 8.5.4.16 (DFh) VREF_TRANSITION_RATE
        17. 8.5.4.17 (F0h) SLOPE_COMPENSATION
        18. 8.5.4.18 (F1h) ISENSE_GAIN
        19. 8.5.4.19 (FCh) DEVICE_CODE
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Internal Operation Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Component Selection
            1. 9.2.1.2.1.1 Output Inductor Selection
            2. 9.2.1.2.1.2 Output Capacitor Selection
          2. 9.2.1.2.2 Internal Operation With Some Switchers Disabled
          3. 9.2.1.2.3 Internal Operation With All Switchers Enabled
          4. 9.2.1.2.4 Example Configuration
          5. 9.2.1.2.5 Unused Switchers
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Current Sharing Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing Timing Example
      3. 9.2.3 External Sequencing Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 External Sequencing Through PG Pins
          2. 9.2.3.2.2 External Sequencing Through SW
          3. 9.2.3.2.3 Example Configuration
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
      2. 12.1.2 Related Parts
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
TPS65400-Q1 po_SLVSCQ9.gif
A. Thermal pad must be soldered to PCB as SW3 and SW4 power ground

Pin Functions

PIN DESCRIPTION
NAME NO.
CB1 1 Bootstrap pin for high-side MOSFET gate drive for SW1
SW1 2 Switch pin for SW1
3
4
PVIN1 5 Power input for buck switching regulator SW1
PVIN2 6 Power input for SW2
PGND1 7 Power ground for buck converters
PGND2 8 Power ground for buck converters
SW2 9 Switch pin for SW2
10
11
CB2 12 Bootstrap pin for SW2 high-side MOSFET gate drive
ENSW2 13 Enable input pin for SW2. Active high. 2-µA internal pullup current is inside.
VFB2 14 Feedback input pin for SW2
COMP2 15 Compensation pin for external compensation network for SW2. Pulling this line high to VDDD configures the SW1 controller to control both SW1 and SW2.
SS2/PG2 16 Soft-start for SW2 (default). A capacitor is used to set the startup time. This pin can also be reconfigured through I2C to display the PGOOD2 signal instead.
PGOOD 17 Default PGOOD signal is for all switchers. It can be changed according to (D2h) PIN_CONFIG_00. If all switchers are disabled, PGOOD is low.
VDDG 18 Supply for gate drives. Bypass locally to PGND.
VDDA 19 Output of internal regulator for analog controls.
VDDD 20 3.3-V output of internal regulator digital controls
AGND 21 Ground connection for analog controls
VIN 22 Analog VIN. Power input pin for VDDD, VDDA, and VGATE subregulator power
CE 23 Chip enables. Internal pull-up current will default to high if the pin is left floating. Connect to an open-drain output to pull low to disable. Driving with a push-pull output is not recommended. When low, internal regulators are shutdown to minimize power, and functionsa are disabled. Configuration is reloaded from EEPROM as part of the power-up sequence when CE goes high.
SS3/PG3 24 Soft-start for SW3 (default). A capacitor is used to set the startup time. This pin can also be reconfigured through I2C to display the PGOOD3 signal instead.
COMP3 25 Compensation pin for external compensation network for SW3
VFB3 26 Feedback input pin for SW3
ENSW3 27 Enable input pin for SW3. Active high. 2-µA internal pullup current is inside.
CB3 28 Bootstrap pin for SW3 high-side MOSFET gate drive
SW3 29 Switch pin for SW3. Max rated output current is 2 A.
PVIN3 30 Power input for buck switching regulator SW3
PVIN4 31 Power input for SW4
SW4 32 Switch pin for SW4. Max rated output current is 2 A.
CB4 33 Bootstrap pin for SW4 high-side MOSFET gate drive
ENSW4 34 Enable input pin for SW4. Active high. 2-µA internal pullup current is inside.
VFB4 35 Feedback input pin for SW4
COMP4 36 Compensation pin for external compensation network for SW4. Pulling this line high to VDDD configures the SW3 controller to control both SW3 and SW4.
SS4/PG4 37 Soft-start for SW4 (default). A capacitor is used to set the startup time. This pin can also be reconfigured through I2C to display the PGOOD4 signal instead
I2CADDR 38 Select I2C address with resistor to AGND
RST_N 39 Reset of digital logic. When low, all switchers are disabled. Configuration is reloaded from EEPROM when RESET_N is deasserted.
RCLOCK_SYNC 40 Resistor for setting master clock frequency from 275 kHz to 2.2 MHz or for clock sync
I2CALERT 41 Open-drain output that is pulled low for 200 µs when a timeout condition is detected by the I2C watchdog on either SDA or SCL.
SDA 42 Data input/output pin for I2C bus
SCL 43 Clock input pin for I2C bus
CLK_OUT 44 Clock output signal. Open-collector output, requires pull up.
SS1/PG1 45 Soft-start for SW1 (default). A capacitor is used to set the startup time. This pin can also be reconfigured through I2C to display the PGOOD1 signal instead.
COMP1 46 Compensation pin for external compensation network for SW1
VFB1 47 Feedback input pin for SW1
ENSW1/ENSEQ 48 Enable input pin for SW1. Active high. 2-µA internal pullup current is inside.