JAJSFE5C October   2009  – May 2018 TPS65720 , TPS65721

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions—DSBGA (TPS65720)
    2.     Pin Functions—DSBGA (TPS657201, TPS657202)
    3.     Pin Functions—WQFN (TPS65721)
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Dissipation Ratings
    7. 8.7 Timing Requirements
    8. 8.8 Switching Characteristics
    9. 8.9 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  Battery Charger and Power Path
      2. 9.3.2  Power-Path Management
      3. 9.3.3  Battery Charging
        1. 9.3.3.1 I-PRECHARGE
        2. 9.3.3.2 ITERM
        3. 9.3.3.3 Battery Detection and Recharge
        4. 9.3.3.4 Charge Termination On/Off
        5. 9.3.3.5 Timers
        6. 9.3.3.6 Dynamic Timer Function
        7. 9.3.3.7 Charger Fault
      4. 9.3.4  Thermal Regulation and Thermal Shutdown
      5. 9.3.5  Battery Pack Temperature Monitoring
      6. 9.3.6  DCDC1 Converter
      7. 9.3.7  Power Save Mode
        1. 9.3.7.1 Dynamic Voltage Positioning
        2. 9.3.7.2 Soft Start
        3. 9.3.7.3 100% Duty Cycle Low Dropout Operation
        4. 9.3.7.4 Undervoltage Lockout
      8. 9.3.8  Short-Circuit Protection
      9. 9.3.9  Thermal Shutdown
      10. 9.3.10 LDO1
        1. 9.3.10.1 Default Voltage Setting for LDOs and DCDC1
        2. 9.3.10.2 Internal Analog Multiplexer (BAT, TS, TS_OUT); TPS657201, TPS657202 Only
        3. 9.3.10.3 Internal Battery Voltage Comparator
        4. 9.3.10.4 GPIOs, LED Drivers
        5. 9.3.10.5 RESET Output
        6. 9.3.10.6 Threshold Input (TPS65721 Only)
          1. 9.3.10.6.1 ENABLE for DCDC1 and LDO1
          2. 9.3.10.6.2 PB_IN Input
          3. 9.3.10.6.3 HOLD_DCDC1 Input
          4. 9.3.10.6.4 HOLD_LDO1 Input
          5. 9.3.10.6.5 INT Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Down
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Power-On Reset Mode
      5. 9.4.5 Idle Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1  CHGSTATUS Register Address: 01h (read only)
      2. 9.6.2  CHGCONFIG0 Register Address: 02h (read/write)
      3. 9.6.3  CHGCONFIG1 Register Address: 03h (read/write)
      4. 9.6.4  CHGCONFIG2 Register Address: 04h (read/write)
      5. 9.6.5  CHGCONFIG3 Register Address: 05h (read/write)
      6. 9.6.6  CHGSTATE Register Address: 06h (read only)
      7. 9.6.7  DEFDCDC1 Register Address: 07h (read/write)
      8. 9.6.8  LDO_CTRL Register Address: 08h (read/write)
      9. 9.6.9  CONTROL0 Register Address: 09h (read/write)
      10. 9.6.10 CONTROL1 Register Address: 0Ah (read/write)
      11. 9.6.11 GPIO_SSC Register Address: 0Bh (read/write)
      12. 9.6.12 GPIODIR Register Address: 0Ch (read/write)
      13. 9.6.13 IRMASK0 Register Address: 0Dh (read/write)
      14. 9.6.14 IRMASK1 Register Address: 0Eh (read/write)
      15. 9.6.15 IRMASK2 Register Address: 0Fh (read/write)
      16. 9.6.16 IR0 Register Address: 10h (read only)
      17. 9.6.17 IR1 Register Address: 11h (read)
      18. 9.6.18 IR2 Register Address: 12h (read)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Voltage Setting
          1. 10.2.2.1.1 DCDC1
          2. 10.2.2.1.2 LDO1
        2. 10.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 10.2.2.2.1 Inductor Selection
          2. 10.2.2.2.2 Output Capacitor Selection
          3. 10.2.2.2.3 Input Capacitor Selection
        3. 10.2.2.3 Charger/Power Path
          1. 10.2.2.3.1 Charger Stability
          2. 10.2.2.3.2 Setting the Charge Current
          3. 10.2.2.3.3 Dynamic Power Path Management (DPPM)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

VSYS = 3.6 V, VDCDC1 = 2.05 V, PFM mode, L = 3.3 μH, COUTDCDC1 = 4.7 μF, VINLDO1 = 2.05 V, VLDO1 = 1.85 V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ Operating quiescent current when only DCDC1 converter is enabled DCDC1 enabled, IOUT = 0 mA. PFM mode enabled; device not switching 36 45 μA
DCDC1 enabled, IOUT = 0 mA. PWM mode 2.8 mA
IQ Operating quiescent current when LDO1 and DCDC1 are enabled Current into BAT pin (PFM mode) 33 50 μA
Current into VINLDO1 13 18 μA
ISD Shutdown current after voltage was applied to BAT but device never enabled before (shipping mode) For VINLDO1 = 0 V (LDO1 supplied by DCDC1); powered by VBAT = 3.6 V 4 13 μA
Shutdown current after first power-up For VINLDO1 = 0 V (LDO1 supplied by DCDC1); powered by VBAT = 3.6 V 12 17 μA
Shutdown current after first power-up For VINLDO1 ≠ 0 V (LDO1 supplied by SYS); powered by VBAT = 3.6 V 12 18 μA
SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD
VIH High-level input voltage for SCLK, SDAT, GPIOx, HOLD_DCDC1, HOLD_LDO1, PB_IN GPIOs configured as input 1.2 VSYS V
VIL Low-level input voltage for SCLK, SDAT, GPIOx, HOLD_DCDC1, HOLD_LDO1, PB_IN GPIOs configured as input 0 0.4 V
VOL Low-level output voltage for SDAT, GPIOx, INT, RESET GPIOs configured as output; Io = 1 mA; no internal pull-up 0 0.4 V
IOL Sink current for GPIO2, GPIO3 GPIO2, GPIO3 configured as current sink; VOL = 0.4 V ;
for TJ = 0°C to 85°C		 –20% 5 20% mA
Sink current for GPIOx GPIOx configured as open-drain output ; output = LOW 3 mA
VOL Minimum voltage for proper current regulation from GPIO2 or GPIO3 to GND if programmed as a current sink IO = 5 mA; current sink turned on 0.4 V
VRESET-falling LDO1 out of regulation reset voltage Falling edge; RESET is asserted LOW for TPS65720, TPS657201, TPS657202 VLDO1, nom-13% VLDO1,
nom-7%		 V
VRESET-rising Rising edge; RESET is released HIGH for TPS65720, TPS657201, TPS657202 after TRESET VLDO1,
nom-4%		 V
VTHRESHOLD_down Threshold voltage for reset input Falling voltage; WQFN package only –3% 570 3% mV
VTHRESHOLD_hys Hysteresis on THRESHOLD Rising voltage; WQFN package only 30 mV
ILKG Input leakage current PB_IN, SDAT, SCLK, GPIOx configured as output, INT, RESET, output high impedance 0.2 μA
STEP-DOWN CONVERTER
VSYS Input voltage for DCDC1 2.3 5.6 V
UVLO Internal undervoltage lockout threshold hysteresis VSYS falling 2.15 2.2 2.25 V
VSYS rising 120 mV
POWER SWITCH
RDS(ON) High-side MOSFET ON-resistance VSYS = VINDCDC1 = 3.6 V, YFF package 350 600 mΩ
VSYS = VINDCDC1 = 3.6 V, RSN package 400 650
ILK_HS High-side MOSFET leakage current VDS = 5.6 V 1 μA
RDS(ON) Low-side MOSFET ON-resistance VINDCDC1/2 = 3.6 V, YFF package 300 500 mΩ
VINDCDC1/2 = 3.6 V, RSN package 350 550 mΩ
ILK_LS Low-side MOSFET leakage current VDS = 5.6 V 1 μA
ILIMF Forward current limit high-side and low-side MOSFET 2.3 V ≤ VIN ≤ 5.6 V, TPS65720 425 600 775 mA
2.3 V ≤ VIN ≤ 5.6 V, TPS65721, TPS657201, TPS657202 625 850 1150 mA
IO DC output current VSYS > 2.7 V; TPS65720 200 mA
VSYS > 2.7 V; TPS65721, TPS657201, TPS657202 400
OUTPUT
VOUT Output voltage range 0.6 Vin V
VFB Feedback voltage for TPS65720, TPS65721 0.6 V
VOUT Default output voltage for TPS657201 1.85 V
VOUT Default output voltage for TPS657202 1.90 V
IFB FB pin input current for externally adjustable version External resistor-divider 0.1 μA
IFB FB pin input current for TPS657201, TPS657202 Internal resistor-divider 5 μA
VOUT DC output voltage accuracy (1) VIN = 2.3 V to 5.6 V; PFM operation, 0 mA < IOUT < IOUTMAX 1% 3%
VIN = 2.3 V to 5.6 V, PWM operation, 0 mA < IOUT < IOUTMAX –2% 2%
DC output voltage load regulation PWM operation 0.5 %/A
VPGOOD-falling PGOOD threshold at falling output voltage <PGOODZ_DCDC1> is set to 1 VDCDC1,
nom-14%		 VDCDC1,
nom-7%		 V
VPGOOD-rising PGOOD threshold at rising output voltage <PGOODZ_DCDC1> is set to 0 VDCDC1,
nom-5%		 V
RDIS Internal discharge resistor at L DCDC1 disabled; the discharge function can be disabled as an EEPROM option 300 400 Ω
THERMAL PROTECTION FOR DCDC1 AND LDO1
TSD Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 30 °C
VLDO1 LOW DROPOUT REGULATOR
VINLDO Input voltage range for LDO1 1.8 5.6 V
VLDO1 LDO1 output voltage range 0.8 3.3 V
VLDO1 LDO1 output voltage Default output voltage for TPS65720, TPS657201 1.85 V
VLDO1 LDO1 output voltage Default output voltage for TPS657202 2.85 V
VFB_LDO1 Feedback voltage Externally adjustable version only: TPS65721 0.8 V
IFB_LDO1 FB pin input current 0.1 μA
IO Output current for LDO1 200 mA
ISC LDO1 short circuit current limit VLDO1 = GND; VINLDO1 = 2.05 V 350 500 mA
Dropout voltage at LDO1, YFF package IO = 200 mA, VINLDO = 2.05 V 180 mV
Dropout voltage at LDO1, RSN package IO = 200 mA, VINLDO = 2.05 V 120 mV
Output voltage accuracy for LDO1 IO = 200 mA –1.5% 2.5%
Line regulation for LDO1 VINLDO1 = VLDO1 + 0.5 V (min. 1.8 V) to 5.6 V (VSYS),
IO = 50 mA		 –1% 1%
Load regulation for LDO1 IO = 0 mA to 200 mA for LDO1 –1% 2%
RDIS Internal discharge resistor at VLDO1 LDO disabled, discharge function per default disabled in register 250 400 Ω
BATTERY VOLTAGE AND BATTERY TEMPERATURE MONITOR WITH MULTIPLEXER; INTERNAL BATTERY VOLTAGE COMPARATOR
VTS Input voltage range on TS pin for full scale output on pin TS_OUT
(0 V to 1.4 V)		 Equals –20°C to 60°C on a 10k NTC 0 1.4 V
VBAT Input voltage range on BAT pin for full scale output on pin TS_OUT
(0 V to 1.4 V)		 2.2 4.5 V
VTS_OUT Output voltage range on pin TS_OUT ITS_OUT = 0 mA 0 1.4 V
0 < ITS_OUT < 0.05 mA 0.06 1.4
Offset error on pin TS_OUT In temperature-sense mode; VO with Vbat = 2.2 V ±7.5 mV
SR Slew rate VTS_OUT; 0 V to 1.4 V 1 V/ms
ITS_OUT_SC Short circuit current 0.1 mA
Load capacitance Maximum capacitance at TS_OUT 100 pF
Battery voltage comparator threshold voltage Depending on Bits <VBAT0>, <VBAT1>; falling voltage –3% 3% V
Battery voltage comparator threshold voltage hysteresis Rising voltage 200 mV
ACCURACY
VBAT MODE
Offset TJ = 10°C to 35°; for V(TS) ≥ 0.2 V –22 22 mV
Gain error TJ = 10°C to 35°; for V(TS) ≥ 0.2 V –11 11 mV
Offset TJ = –40°C to 85°C; for V(TS) ≥ 0.2 V –30 30 mV
Gain error TJ = –40°C to 85°C; for V(TS) ≥ 0.2 V –14 14 mV
TS MODE
Internal TS resistor (for 10k NTC, B=3380) TJ = 25°C –1.5% 29.23 1.5% kΩ
Internal TS resistor (for 100k NTC) TJ = 25°C –1.5% 292.3 1.5% kΩ
Internal TS resistor temperature drift TJ = –40°C to 85°C –4.5%
Internal V2V0 reference voltage TJ = –40°C to 85°C –1.2% 2 1.2% V
POWER PATH
VUVLO Undervoltage lockout VAC: 0 V → 4 V 3.2 3.3 3.45 V
VHYS-UVLO Hysteresis on UVLO VAC: 4 V → 0 V 200 300 mV
VIN-DT Input power detection threshold (Input power detected if VIN > VBAT + VIN-DT) VBAT = 3.6 V,
VIN: 3.5 V → 4 V		 40 80 140 mV
VHYS-INDT Hysteresis on VIN-DT VBAT = 3.6 V, VIN: 4 V → 3.5 V 20 mV
VOVP Input overvoltage protection threshold VAC: 5 V → 7 V 6.4 6.6 6.8 V
VHYS-OVP Hysteresis on OVP VAC: 11 V → 5 V 105 mV
VDO(AC-SYS) AC pin to SYS pin dropout voltage
VAC – VSYS 		ISYS = 0.3 A, VAC = 4.35 V, VBAT = 4.2 V; YFF package 170 285 mV
ISYS = 0.3 A, VAC = 4.35 V, VBAT = 4.2 V; RSN package 210 325 mV
VDO(BAT-SYS) Battery to SYS pin dropout voltage
VBAT – VSYS 		ISYS = 0.2 A, VAC = 0 V, VBAT > 3 V; YFF package 80 mV
ISYS = 0.2 A, VAC = 0 V, VBAT > 3 V; RSN package 120 mV
VSYS(REG) SYS pin voltage regulation selectable register <CHGCONFIG0> Bits <VSYS1>; <VSYS0> 00: VAC > VSYS + VDO(AC-SYS), VBAT < 3.3V –5% 3.4 5% V
00: VAC > VSYS + VDO(AC-SYS), VBAT ≥ 3.3 V –5% VBAT +
200 mV		 5%
01: VAC > VSYS + VDO(AC-SYS) –5% 4.4 5%
10: VAC > VSYS + VDO(AC-SYS) –5% 5.0 5%
11: VAC > VSYS + VDO(AC-SYS) –5% 5.5 5%
IAC-MAX Maximum Input Current Register <CHCONFIG0> Bit <AC input current1, AC input current0> = 00 90 95 100 mA
Bit < AC input current1, AC input current0> = 01 or 10 450 475 500
VAC-LOW Input voltage threshold when input current is reduced Input current is reduced if voltage at AC falls below VAC-LOW to keep the AC voltage above 4.5 V 4.35 4.5 4.65 V
VDPM Output voltage threshold when charging current is reduced Bit <V_DPPM> = 1 VO(REG) – 100 mV V
Register <CHCONFIG2> Bit <V_DPPM> = 0 4.3
VBSUP1 Enter battery supplement mode VOUT ≤ VBAT –
40 mV		 V
VBSUP2 Exit battery supplement mode VOUT ≥ VBAT –
20 mV		 V
VO(SC1) Output short-circuit detection threshold, power-on 0.8 0.9 1 V
VO(SC2) Output short-circuit detection threshold, supplement mode
VBAT – VOUT > VO(SC2) indicates short-circuit		 200 250 300 mV
BATTERY CHARGER
QUIESCENT CURRENT
IIACSTDBY) Standby current into AC pin VIN = 5 V; ACinputcurrent[1,0] = 11 60 80 μA
VIN = 28 V; ACinputcurrent[1,0] = 11 530 μA
ICC Active supply current, AC pin VIN = 5 V, no load on DCDC1, LDO1, SYS pin, VSYS[1,0] = 11;
ACinputcurrent[1,0] = 10; CH_EN = 0		 2 mA
IBAT(SC) Source current for BAT pin short-circuit detection 4 7.5 11 mA
VBAT(SC) BAT pin short-circuit detection threshold 1.6 1.8 2.0 V
Vo(BATREG) Battery charger voltage Depending on setting in CHGCONFIG3 And internal EEPROM Default = 4.2 V –1% 4.15 1% V
–1% 4.175 1%
–1% 4.20 1%
–1% 4.225 1%
–1% 4.25 1%
–1% 4.275 1%
–1% 4.30 1%
–1% 4.325 1%
VLOWV Precharge to fast-charge transition threshold 2.9 3.0 3.1 V
QUIESCENT CURRENT (continued)
ICHG Maximum battery fast charge current VBAT(REG) > VBAT > VLOWV, VIN = VAC or VUSB = 5 V 300 mA
Minimum battery fast charge current 10 mA
Battery fast charge current set factor VBAT > VLOWV, VIN = 5 V, IIN-MAX > ICHG, No load on SYS pin, thermal loop not active, DPPM loop not active KISET / RISET A
KISET Fast charge current factor at 300 mA for ICH_SCL[1,0] = 11 (charge current scaling is 100% of ISET value) –15% 450 15% AΩ
at 40 mA for ICH_SCL[1,0] = 11 (charge current scaling is 100% of ISET value) –20% 450 20%
at 225 mA range for ICH_SCL[1,0] = 10 (charge current scaling is 75% of ISET value) –15% 338 15%
at 30 mA for ICH_SCL[1,0] = 10 (charge current scaling is 75% of ISET value) –20% 338 20%
at 150 mA for ICH_SCL[1,0] = 01 (charge current scaling is 50% of ISET value) –10% 225 10%
at 20 mA for ICH_SCL[1,0] = 01 (charge current scaling is 50% of ISET value) –15% 225 15%
at 75 mA for ICH_SCL[1,0] = 00 (charge current scaling is 25% of ISET value) –10% 112 10%
at 10 mA for ICH_SCL[1,0] = 00 (charge current scaling is 25% of ISET value) –20% 112 20%
IPRECHG Precharge current for I_PRE[1,0] = 11 (pre-charge current scaling is 20% of charge current) 0.15 × ICHG 0.2 × ICHG 0.25 × ICHG
for I_PRE[1,0] = 10 (pre-charge current scaling is 15% of charge current) 0.11 × ICHG 0.15 × ICHG 0.19 × ICHG
for I_PRE[1,0] = 01 (pre-charge current scaling is 10% of charge current) 0.07 × ICHG 0.1 × ICHG 0.13 × ICHG
for I_PRE[1,0] = 00 (pre-charge current scaling is 5% of charge current) 0.03 × ICHG 0.05 × ICHG 0.08 × ICHG
ITERM Charge current value for termination detection threshold (internally set) for I_TERM[1,0] = 11 (termination current is 20% of charge current) 0.15 × ICHG 0.2 × ICHG 0.27 × ICHG
for I_TERM[1,0] = 10 (termination current is 15% of charge current) 0.11 × ICHG 0.15 × ICHG 0.21 × ICHG
for I_TERM[1,0] = 01 (termination current is 10% of charge current) 0.07 × ICHG 0.1 × ICHG 0.15 × ICHG
for I_TERM[1,0] = 00 (termination current is 5% of charge current) 0.03 × ICHG 0.05 × ICHG 0.08 × ICHG
VRCH Recharge detection threshold Voltage below nominal charger voltage 165 100 60 mV
IBAT(DET) Sink current for battery detection 5 7.5 10 mA
TCHG Charge safety timer Safety timer range selectable by I2C; default setting without DPPM or thermal loop active –35% 5 35% h
TPRECHG Pre-charge timer Pre-charge timer range; default setting –35% 30 35% min
BATTERY-PACK NTC MONITOR
RNTCHOT Thermistor high temperature detection resistance (equals 45°C for 10-kΩ NTC; B = 3380) Hot temperature detected and charging suspended when the resistance of the battery-NTC is lower than RNTCHOT 4.3 5 5.7 kΩ
Thermistor high temperature detection resistance (equals 50°C for 10-kΩ NTC; B = 3380) 3.5 4.1 4.8 kΩ
Thermistor high temperature detection resistance (equals 55°C for 10-kΩ NTC; B = 3380 ) 2.9 3.5 4.2 kΩ
Thermistor high temperature detection resistance (equals 60°C for 10-kΩ NTC; B = 3380) 2.4 3 3.5 kΩ
Thermistor high temperature detection resistance (equals 45°C for 100-kΩ NTC) 43 50 57 kΩ
Thermistor high temperature detection resistance (equals 50°C for 100-kΩ NTC) 35 41 48 kΩ
Thermistor high temperature detection resistance (equals 55°C for 100-kΩ NTC) 29 35 42 kΩ
Thermistor high temperature detection resistance (equals 60°C for 100-kΩ NTC) 24 30 35 kΩ
RNTCCOLD Thermistor low temperature detection resistance (equals 0°C for 10-kΩ NTC; B = 3380) Cold temperature detected and charging suspended when the resistance of the battery-NTC is higher than RNTCCOLD 25 27 30 kΩ
Thermistor low temperature detection resistance (equals 5°C for 10-kΩ NTC; B = 3380) 20 22 24 kΩ
Thermistor low temperature detection resistance (equals 10°C for 10-kΩ NTC; B = 3380 ) 16 18 20 kΩ
Thermistor low temperature detection resistance (equals 15°C for 10-kΩ NTC; B = 3380) 13 15 16 kΩ
Thermistor low temperature detection resistance (equals 0°C for 100-kΩ NTC) 250 270 300 kΩ
Thermistor low temperature detection resistance (equals 5°C for 100-kΩ NTC) 200 220 240 kΩ
Thermistor low temperature detection resistance (equals 10°C for 100-kΩ NTC) 160 180 200 kΩ
Thermistor low temperature detection resistance (equals 15°C for 100-kΩ NTC) 130 150 160 kΩ
VHYS(COLD) Low temperature trip point hysteresis For 10-kΩ NTC; B = 3380 5 °C
RNOSENSOR Thermistor not detected for 10k NTC Hot temperature detected and charging suspended when the resistance of the battery-NTC is higher than RNOSENSOR 260 340 620 kΩ
Thermistor not detected for 100k NTC 2500 3400 6200 kΩ
THERMAL REGULATION
TJ(REG) Lower Temperature regulation limit 115 °C
TJ(REG) Upper Temperature regulation limit 135 °C
TJ(OFF) Thermal shutdown temperature 155 °C
TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C
(1) Output voltage specification does not include tolerance of external voltage programming resistors.