JAJSFE5C October 2009 – May 2018 TPS65720 , TPS65721
PRODUCTION DATA.
IR1 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | BO |
---|---|---|---|---|---|---|---|---|
Bit name and function | CH_SLEEP | CH_RESET | CH_IDLE | CH_PRECH | CH_CC_CV | CH_LDO | CH_FAULT | CH_SUSP |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Default value loaded by: | UVLO/R | UVLO/R | UVLO/R | UVLO/R | UVLO/R | UVLO/R | UVLO/R | UVLO/R |
Set by: | Rising edge of CH_SLEEP | Rising edge of CH_RESET | Rising edge of CH_IDLE | Rising edge of CH_PRECH | Rising edge of CH_CC_CV | Rising edge of CH_LDO | Rising edge of VBAT_FAULT* | Rising edge of TH_SUSP |
Read/write | R | R | R | R | R | R | R | R |
Bit 7..0 | interrupt register:
0 = no interrupt 1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK1 |