JAJSEF7G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 デバイス・サポート
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 ドキュメントのサポート
      1. 9.2.1 関連資料
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 Community Resources
    5. 9.5 商標
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Layout Guidelines

As in every switch-mode-supply design, the following general layout rules apply:

  • Use a solid ground-plane for power-ground (PGND)
  • Use an independent ground for Logic, LDOs and Analog (AGND)
  • Connect those Grounds at a star-point ideally underneath the device.
  • Place input capacitors as close as possible to the input-pins of the device. This is paramount and more important than the output-loop!
  • Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the device.
  • Keep the loop-area formed by Phase-node, Inductor, output-capacitor and PGND as small as possible.
  • For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide traces, avoid switching layers but if needed, use plenty of vias.

The goal of the previously listed guidelines is a layout that minimizes emissions, maximizes EMI-immunity, and maintains a safe operating area for the device.

To minimize the spiking at the phase-node for both, high-side (VIN – SWx) as well as low-side (SWx – PGND), the decoupling of VIN is paramount. Appropriate decoupling and thorough layout should ensure that the spikes never exceed 7V across the high-side and low-side FETs.

TI recommends the guidelines shown in Figure 8-1 regarding parasitic inductance and resistance.

TPS659037 layout_parasitic_slis165.gifFigure 8-1 Parasitic Inductance and Resistance

Table 8-1 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable values in an optimized layout.

Table 8-1 Maximum Allowable Parasitic

CONNECTION MAXIMUM ALLOWABLE INDUCTANCE MAXIMUM ALLOWABLE RESISTANCE OPTIMIZED LAYOUT (EVM) INDUCTANCE OPTIMIZED LAYOUT (EVM) RESISTANCE
PowerPlane – CIN N/A N/A for SOA, keep small for efficiency N/A N/A for SOA, keep small for efficiency
CIN – SMPSx_IN 1 nH 3 mΩ SMPS1 0.533 nH SMPS1 1.77 mΩ
SMPS2 0.465 nH SMPS2 1.22 mΩ
SMPS3 0.494 nH SMPS3 1.37 mΩ
SMPS4 0.472 nH SMPS4 1.23 mΩ
SMPS5 0.517 nH SMPS5 1.27 mΩ
SMPS6 0.518 nH SMPS6 1.69 mΩ
SMPS7 0.501 nH SMPS7 1.27 mΩ
SMPS8 0.509 nH SMPS8 1.42 mΩ
SMPS9 0.491 nH SMPS9 1.4 mΩ
CIN – SMPSx_GND 1 nH 2 mΩ SMPS1 0.552 nH SMPS1 1.21 mΩ
SMPS2 0.583 nH SMPS2 0.8 mΩ
SMPS3 0.668 nH SMPS3 0.93 mΩ
SMPS4 0.57 nH SMPS4 0.81 mΩ
SMPS5 0.577 nH SMPS5 0.76 mΩ
SMPS6 0.608 nH SMPS6 1.13 mΩ
SMPS7 0.646 nH SMPS7 0.83 mΩ
SMPS8 0.67 nH SMPS8 0.73 mΩ
SMPS9 0.622 nH SMPS9 0.82 mΩ
SMPSx_SW – Inductor N/A N/A for SOA, keep small for efficiency N/A SMPS1 1.9 mΩ
SMPS2 0.89 mΩ
SMPS3 1.99 mΩ
SMPS4 0.93 mΩ
SMPS5 1.37 mΩ
SMPS6 1.11 mΩ
SMPS7 1.17 mΩ
SMPS8 1.35 mΩ
SMPS9 0.88 mΩ
Inductor – COUT N/A N/A for SOA, keep small for efficiency N/A N/A for SOA, keep small for efficiency
COUT – GND Use dedicated GND plane to keep inductance low mΩ SMPS1 0.552 nH SMPS1 1.21 mΩ
SMPS2 0.583 nH SMPS2 0.8 mΩ
SMPS3 0.668 nH SMPS3 0.93 mΩ
SMPS4 0.57 nH SMPS4 0.81 mΩ
SMPS5 0.577 nH SMPS5 0.76 mΩ
SMPS6 0.608 nH SMPS6 1.13 mΩ
SMPS7 0.646 nH SMPS7 0.83 mΩ
SMPS8 0.67 nH SMPS8 0.73 mΩ
SMPS9 0.622 nH SMPS9 0.82 mΩ
GND(CIN) – GND(COUT) Use dedicated GND plane to keep inductance low mΩ Use dedicated GND plane to keep inductance low mΩ

TI recommends to measure the voltages across the high-side FET (voltage at SMPSx_IN vs. SMPSx_SW) and the low-side FET (SMPSx_SW vs. SMPSx_GND) with a high-bandwidth high-sampling rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as close as possible to the device-pins and verify the amplitude of the spikes. A small-loop-GND-connection to the closest accessible SMPSx_GND (of the particular rail) is essential. Ideally, this measurement should be performed during start-up of the respective SMPS-rail (to take in account the inrush-current) and at high temperature.

When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a maximum of 7V when measuring at the pins. Similarly, when measuring the voltage difference between the SMPSx_SW and SMPSx_GND pins, there should be a maximum of 7V when measuring at the pins.

For more information on cursor-positioning, see Figure 8-2 and Figure 8-3.

TPS659037 layout_hs_swcs095.gif
Measure across the high-side FET (SMPSx_IN – SMPSx_SW) as close to the IC as possible. The preferred measurement is with a differential probe. The negative side of the probe should be at SMPSx_SW and the positive side of the probe should measure SMPSx_IN. As shown in this image, the voltage across the high-side FET should not exceed 7V. Repeat the measurement for all SMPSs in use.
Figure 8-2 Measuring the High-side FET (Differentially)
TPS659037 layout_ls_swcs095.gif
Measure across the low-side FET (SMPSx_SW – SMPSx_GND) as close to the IC as possible. The preferred measurement is with a differential probe. The negative side of the probe should be at SMPSx_GND and the positive side of the probe should measure SMPSx_SW. As shown in this image, the voltage across the low-side FET should not exceed 7V.Repeat the measurement for all SMPSs in use.
Figure 8-3 Measuring the Low-side FET (Differentially)