JAJSEF7G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 デバイス・サポート
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 ドキュメントのサポート
      1. 9.2.1 関連資料
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 Community Resources
    5. 9.5 商標
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.7 Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators

Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input capacitance (C9, C10, C11, C12, C13) 4.7 µF
Output capacitance (C18, C19, C21, C22)(1) SMPS12 or SMPS45 dual phase operation, per phase 33 47 57 µF
Output capacitance, (C20, C24)(1) SMPS3 and SMPS7 (triple phase operation) 33 47 57 µF
CESR Filtering capacitor ESR 1 MHz ≤ f ≤ 10 MHz 2 10 mΩ
Output filter inductance (L1, L2, L3, L4, L5) SMPSx_SW 0.7 1 1.3 µH
DCRL Filter inductor DC resistance 50 100 mΩ
VSMPSx Input voltage range, SMPSx_IN Connected to VSYS (VCC1) 3.135 5.25 V
VOSMPSx Output voltage, programmable, SMPSx RANGE = 0 (value for RANGE must not be changed when SMPS is active). In Eco-mode the output voltage values are fixed (defined before Eco-mode is enabled). RANGE = 1 is not supported for Multi-phase regulators. 0.7 1.65 V
Step size, 0.7 V ≤ VO ≤ 1.65 V (RANGE = 0) 10 mV
DC output voltage accuracy, includes voltage references, DC load/line regulation, process and temperature Eco-mode –3% 4%
Forced PWM mode –1% 2%
Ripple, dual phase Maximum load, VI = 3.8 V, VO = 1.2 V, ESRCO = 2 mΩ, measure with 20-MHz LPF 4 mVPP
Ripple, triple phase Maximum load, VI = 3.8 V, VO = 1.2 V, ESRCO = 2 mΩ, measure with 20-MHz LPF 1 mVPP
ΔVO(ΔVI) DC line regulation 0.1 %/V
ΔVO(ΔIO) DC load regulation 0.1 %/A
Transient load step response, dual phase IO = 0.8 to 2 A, tr = tf = 400 ns, CO = 47 µF , L= 1 µH 3%
Transient load step response, triple phase IO = 0.8 to 2 A, tr = tf = 400 ns, CO = 47 µF , L= 1 µH 3%
Transient load step response, dual or triple phase IO = 0.5 to 500 mA, tr = tf = 100 ns, CO = 47 µF , L= 1 µH 3%
IOmax Rated output current, SMPS12 Advance thermal design is required to avoid thermal shutdown 6 A
Rated output current, SMPS123 Advance thermal design is required to avoid thermal shutdown 9
Rated output current, SMPS45 Advance thermal design is required to avoid thermal shutdown 4
Maximum output current, Eco-mode 5 mA
I(LIM_HS_FET) High-side MOSFET forward current-limit SMPS123, each phase 3.7 4 A
SMPS45, each phase 2.7 3
I(LIM_LS_FET) Low-side MOSFET forward current-limit SMPS123, each phase 3.7 A
SMPS45, each phase 2.7
Low-side MOSFET negative current-limit SMPS123, phase 1 0.6 A
SMPS45, phase 4 0.6
rDS(on_HS_FET) N-channel MOSFET on-resistance, high-side FET SMPS123, each phase 115 mΩ
SMPS45, each phase 115
rDS(on_LS_FET) N-channel MOSFET on-resistance, low-side FET SMPS123, each phase 30 mΩ
SMPS45, each phase 30
t(start) Time from enable to start of the ramp 150 µs
t(ramp) Time from enable to 80% of VO CO < 57 µF per phase, no load 400 1000 µs
Overshoot during turnon 5%
Output voltage slew rate Fixed TSTEP 2.5 mV/μs
R(DIS) Pulldown discharge resistance at SMPS2, SMPS4 output SMPS turned off 300 Ω
SMPSx_SW, SMPS turned off. Pulldown is at the master phase output. 9 22
R(SENSE) Input resistance for remote sense/sense line Between SMPS1_2_FDBK, SMPS1_2_FDBK_GND 380 1300 kΩ
Between SMPS4_5_FDBK, SMPS4_5_FDBK_GND 380 1300
SMPS3_FDBK input resistance 380 1300
IQ(off) Quiescent current – OFF mode IL = 0 mA 0.1 1 µA
IQ(on) Quiescent current -ON mode, dual or triple phase Eco-mode, device not switching, VO < 1.8 V 13.5 19 µA
Eco-mode, device not switching, VO ≥ 1.8 V 15 21
FORCED_PWM mode, IL= 0 mA, VI = 3.8 V, device switching, 1-phase operation 11 mA
VSMPSPG Powergood threshold SMPS output voltage rising, referenced to programmed output voltage –7.5%
SMPS output voltage falling, referenced to programmed output voltage –12.5%
IL_AVG_COMP Powergood: GPADC monitoring SMPS IL_AVG_COMP_rising IOmax – 20% IOmax IOmax + 20%
IL_AVG_COMP_falling, 3-A phase IL_AVG_COMP_rising – 5%
IL_AVG_COMP_falling, 2-A phase IL_AVG_COMP_rising – 8%
(1) Additional information about how this parameter is specified is located in Section 6.2.2.