JAJSEF7G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 デバイス・サポート
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 ドキュメントのサポート
      1. 9.2.1 関連資料
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 Community Resources
    5. 9.5 商標
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

Figure 3-1 169-Pin ZWS New Fine Pitch Ball Grid Array (NFBGA) With 0,8-mm Pitch
Top View

Pin Functions

PIN I/O PU OR PD(2) CONNECTION IF NOT USED OR NOT AVAILABLE DESCRIPTION
NO. NAME
A1 PBKG — — Ground Substrate ground
A2 OSC16MOUT O — Floating 16-MHz crystal oscillator output or floating in case of digital clock
A3 OSC16MIN I — Floating or ground in bypass mode 16-MHz crystal oscillator input or digital clock input
A4 REFGND1 — — Ground System reference ground
A5 LDO9_OUT O — Floating LDO9 output voltage
A6 LDO12_IN I — System supply Power input voltage for LDO1 and LDO2 regulators
A7 GND_ANA — — Ground Analog power ground
A8 LDOVRTC_OUT O — — Internal LDOVRTC output voltage. For silicon revisions 1.3 or earlier, rapid power off and on requires a pulldown resistor on the LDOVRTC_OUT pin. See Section 5.4.11 for more details.
A9 LDOUSB_IN2 I — System supply Power input voltage 2 for LDOUSB regulator
A10 LDOUSB_IN1 I — System supply Power input voltage 1 for LDOUSB regulator
A11 VCC_SENSE2 I — System supply System-supply sense line
A12 GPIO_2 I/O PPU Floating Primary function: General-purpose input(1) or output
PPD
O — Secondary function: REGEN2 — External regulator enable output 2
A13 PBKG — — Ground Substrate ground
B1 SMPS7_FDBK I — Floating Output voltage-sense (feedback) input for step-down converter, SMPS7
B2 GPADC_IN0 I — Ground Sigma-delta GPADC input 0
B3 VCC_SENSE I — System supply System-supply sense line
B4 GPADC_VREF O — Floating Sigma-delta GPADC output reference voltage
B5 LDOLN_OUT O — Floating Output voltage for the low-noise dropout regulator, LDOLN
B6 LDO2_OUT O — Floating LDO2 output voltage
B7 VBG O — — Bandgap reference voltage
B8 SYNCDCDC I — Ground Sync pin to sync DC-DCs with external clock
B9 LDOUSB_OUT O — Floating LDOUSB output voltage
B10 PBKG — — Ground Substrate ground
B11
B12 GPIO_0 I/O PPD Ground or VSYS (VCC1) General-purpose input(1) or output
B13 SMPS1_2_FDBK I — Ground Output voltage-sense (feedback) input for step-down converters, SMPS1 and SMPS2
C1 OSC16MCAP O — Floating Filtering capacitor for the 16-MHz crystal oscillator
C2 GPADC_IN1 I — Ground Sigma-delta GPADC input 1
C3 GPADC_IN2 I — Ground Sigma-delta GPADC input 2
C4 LDO9_IN I — System supply Power input voltage for LDO9 regulator
C5 LDOLN_IN I — System supply Power input voltage for the low-noise dropout regulator, LDOLN
C6 LDO1_OUT O — Floating LDO1 output voltage
C7 VCC1 I — System supply Analog input voltage supply
C8 LDOVANA_OUT O — — Internal LDOVANA output voltage
C9 NC — — — Not connected
C10 GPIO_5 I/O PPU Ground Primary function: General-purpose input(1) or output
PPD(1)
O — Floating Secondary function: CLK32KGO1V8 — 32-kHz digital-gated output clock available when VRTC is present
C11 RPWRON I PU Floating External remote switch-on event
C12 SMPS1_2_FDBK_GND I — Ground Ground-sense (feedback) input for step-down converters, SMPS1 and SMPS2
C13 GPIO_1 I/O PPU Floating Primary function: General-purpose input(1) or output
O PPD Secondary function: VBUSDET - VBUS detection
D1 SMPS7_SW O — Floating Switch node of step-down converter, SMPS7. Connect the output to an inductor.
D2
D3
D4 SMPS7_GND — — Ground Power ground connection for step-down converter, SMPS7
D5
D6 PBKG — — Ground Substrate ground
D7
D8 VBUS I — Ground VBUS Detection Voltage
D9 VIO_IN I — System supply Digital supply input for GPIOs and I/O supply voltage
D10 SMPS1_GND — — Ground Power ground connection for step-down converter, SMPS1
D11 SMPS1_IN I — System supply Power input for step-down converter, SMPS1
D12
D13
E1 SMPS7_IN I — System supply Power input for step-down converter, SMPS7
E2
E3
E4 SMPS7_GND — — Ground Power ground connection for step-down converter, SMPS7
E5 NSLEEP I PPU(1) Floating NSLEEP request signal
PPD
E6 NRESWARM I PPU(1) Floating Warm reset input
E7 GND_ANA — — Ground Analog power ground
E8 PBKG — — Ground Substrate ground
E9 SMPS1_GND — — Ground Power ground connection for step-down converter, SMPS1
E10
E11 SMPS1_SW O — Floating Switch node of step-down converter, SMPS1. Connect the output to an inductor.
E12
E13
F1 SMPS4_IN I — System supply Power input for step-down converter, SMPS4
F2
F3
F4 SMPS4_GND — — Ground Power ground connection for step-down converter, SMPS4
F5 GND_ANA — — Ground Analog power ground
F6 PBKG — — Ground Substrate ground
F7
F8 REGEN1 O — Floating External regulator enable output 1
F9 SMPS2_GND — — Ground Power ground connection for step-down converter, SMPS2
F10
F11 SMPS2_SW O — Floating Switch node of step-down converter, SMPS2. Connect the output to an inductor.
F12
F13
G1 SMPS4_SW O – Floating Switch node of step-down converter, SMPS4. Connect the output to an inductor.
G2
G3
G4 SMPS4_GND — — Ground Power ground connection for step-down converter, SMPS4
G5
G6 RESET_OUT O — Floating System reset and power on output (Low → Reset, High → Active or Sleep)
G7 PBKG — — Ground Substrate ground
G8 PWRON I PU Floating External power-on event (on-button switch-on event)
G9 GPIO_7 I/O PPD Ground or VRTC Primary function: General-purpose input(1) or output
I PPD(1) Secondary function: POWERHOLD input
G10 SMPS2_GND — — Ground Power ground connection for step-down converter, SMPS2
G11 SMPS2_IN I — System supply Power input for step-down converter, SMPS2
G12
G13
H1 SMPS5_SW O — Floating Switch node of step-down converter, SMPS5. Connect the output to an inductor.
H2
H3
H4 SMPS5_GND — — Ground Power ground connection for step-down converter, SMPS5
H5
H6 PBKG — — Ground Substrate ground
H7
H8 I2C2_SDA_SDO I/O — Floating DVS I2C serial bidirectional data (external pullup) and SPI data read signal or I2C serial bidirectional data (external pullup)
H9 GPIO_3 I PPD Ground General-purpose input(1) or output
H10 SMPS3_GND — — Ground Power ground connection for step-down converter, SMPS3
H11 SMPS3_IN I — System supply Power input for step-down converter, SMPS3
H12
H13
J1 SMPS5_IN I — System supply Power input for step-down converter, SMPS5
J2
J3
J4 SMPS5_GND — — Ground Power ground connection for step-down converter, SMPS5
J5 ENABLE1 I PPU Floating Peripheral power request input 1
PPD(1)
J6 PBKG — — Ground Substrate ground
J7 POWERGOOD O — Floating Indication signal for valid regulator output voltages
J8 SMPS9_FDBK I — Ground Output voltage-sense (feedback) input for step-down converter, SMPS9
J9 SMPS3_GND — — Ground Power ground connection for step-down converter, SMPS3
J10
J11 SMPS3_SW O — Floating Switch node of step-down converter, SMPS3. Connect the output to an inductor.
J12
J13
K1 INT O — — Maskable interrupt output request to the host processor
K2 SMPS4_5_FDBK I — Ground Output voltage-sense (feedback) input for step-down converters, SMPS4 and SMPS5
K3 SMPS4_5_FDBK_GND I — Ground Ground-sense (feedback) input for step-down converters, SMPS4 and SMPS5
K4 NC — — — Not connected
K5
K6 SMPS6_FDBK I — Ground Output voltage sense (feedback) input for step-down converter, SMPS6
K7 BOOT1 I — Ground or VRTC Boot pin 1 for power-up sequence selection
K8 PWRDOWN I PPD Floating Power-down signal
K9 RESET_IN I PPD Floating Reset input
K10 GPIO_4 I/O PPU Floating Primary function: General-purpose input(1) or output
PPD(1)
O Secondary function: SYSEN1 — External system enable
K11 LDO3_OUT O — Floating LDO3 output voltage
K12 LDO4_OUT O — Floating LDO4 output voltage
K13 SMPS3_FDBK I — Floating Output voltage-sense (feedback) input for step-down converter, SMPS3
L1 I2C1_SCL_SCK I/O — Floating Control I2C serial clock (external pullup) and SPI clock signal
L2 I2C1_SDA_SDI I/O — Floating Control I2C serial bidirectional data (external pullup) and SPI data signal
L3 BOOT0 I — Ground or VRTC Boot pin 0 for power-up sequence selection
L4 NC — — — Not connected
L5 SMPS6_GND — — Ground Power ground connection for step-down converter, SMPS6
L6
L7 SMPS9_GND — — Ground Power ground connection for step-down converter, SMPS9
L8
L9 SMPS8_GND — — Ground Power ground connection for step-down converter, SMPS8
L10
L11 SMPS8_FDBK I — Ground Output voltage-sense (feedback) input for step-down converter, SMPS8
L12 LDO34_IN I — System supply Power input voltage for LDO3 and LDO4 regulators
L13
M1 PBKG — — Ground Substrate ground
M2
M3 I2C2_SCL_SCE I/O — Floating DVS I2C serial clock (external pullup) and SPI enable signal or I2C serial clock (external pullup)
M4 LDO_SUPPLY I — System supply Power input voltage for internal LDO
M5 SMPS6_SW O — Floating Switch node of step-down converter, SMPS6. Connect the output to an inductor.
M6 SMPS6_IN I — System supply Power input for step-down converter, SMPS6
M7 SMPS9_SW O — Floating Switch node of step-down converter, SMPS9 Connect the output to an inductor.
M8 SMPS9_IN I — System supply Power input for step-down converter, SMPS9
M9 SMPS8_IN I — System supply Power input for step-down converter, SMPS8
M10 SMPS8_SW O — Floating Switch node of step-down converter, SMPS8 Connect the output to an inductor.
M11 CLK32KGO O — Floating 32-kHz digital-gated output clock available when VIO_IN input supply is present
M12 GND_DIG — — Ground Digital power ground
M13 GND_ANA — — Ground Analog power ground
N1 PBKG — — Ground Substrate ground
N2 VIO_GND — — Ground Digital ground connection
N3 LDO_SUPPLY I — System supply Power input voltage for internal LDO
N4 LDO_SUPPLY I — System supply Power input voltage for internal LDO
N5 SMPS6_SW O — Floating Switch node of step-down converter, SMPS6. Connect the output to an inductor.
N6 SMPS6_IN I — System supply Power input for step-down converter, SMPS6
N7 SMPS9_SW O — Floating Switch node of step-down converter, SMPS9 Connect the output to an inductor.
N8 SMPS9_IN I — System supply Power input for step-down converter, SMPS9
N9 SMPS8_IN I — System supply Power input for step-down converter, SMPS8
N10 SMPS8_SW O — Floating Switch node of step-down converter, SMPS8 Connect the output to an inductor.
N11 GPIO_6 I/O PPU Ground Primary function: General-purpose input(1) or output
PPD(1)
O — Floating Secondary function: SYSEN2 — External system enable
N12 VPROG I — Ground or floating Primary function: OTP programming voltage
O — Floating Secondary function: TESTV
N13 PBKG — — Ground Substrate ground
(1) Default option
(2) The PU/PD column shows the pullup and pulldown resistors on the digital input lines. The pullup and pulldown resistors are defined as follows:
    PUpullup
    PDpulldown
    PPUsoftware-programmable pullup
    PPDsoftware-programmable pulldown

Table 3-1 Summary of Digital Signals and Some Dedicated Analog Signals

SIGNAL NAME POWER DOMAIN AND TOLERANCE LEVEL I/O INPUT PU/PD (2) OTP PU/PD SELECTION OUTPUT TYPE SELECTION ACTIVE HIGH OR LOW OTP POLARITY SELECTION
PWRON VSYS (VCC1) Input PU fixed N/A (fixed) N/A (input) Low No
RPWRON VSYS (VCC1) Input PU fixed N/A (fixed) N/A (input) Low No
PWRDOWN VRTC, fail-safe
(5.25-V tolerance)		 Input PPD(1)
(Optional External PU)		 Yes N/A (input) Low or high(1) Yes
POWERGOOD VRTC Output N/A (output) N/A (output) Open-drain Low or high(1) Yes
BOOT0 VRTC Input No No N/A (input) Boot conf. No
BOOT1 VRTC Tri-level input PPU or PPD(1) No N/A (input) Boot conf. No
GPIO_0 VRTC, fail-safe
(5.25-V tolerance)		 Input(1) or output PPD(1) Yes Open-drain Low or high No
GPIO_1
(primary function)		 VSYS Input(1) or output PPU/PPD(1) Yes Push-pull(1) or open- drain Low or high No
GPIO_1
secondary function:
VBUSDET		 Output N/A (output) N/A (output) Push-pull(1) or open- drain High
GPIO_2
(primary function)		 VSYS Input(1) or output PPU or PPD(1) Yes Push-pull(1) or open- drain Low or high No
GPIO_2
secondary function:
REGEN2		 Output N/A (output) N/A (output) Push-pull(1) or open- drain High
GPIO_3 VRTC, fail-safe
(5.25-V tolerance)		 Input(1) or output PPD(1) Yes Open-drain Low or high(1) Yes
GPIO_4
(primary function)		 VIO (VIO_IN) Input(1) or output PPU/PPD(1) No Push-pull Low or high No
GPIO_4
secondary function:
SYSEN1		 Output N/A (output) N/A (output) High
GPIO_5
(primary function) 		VRTC Input(1) or output PPU/PPD(1) No Push-pull(1) or open- drain Low or high No
GPIO_5
secondary function:
CLK32KGO1V8 or SYNCCLKOUT		 Output N/A (output) N/A (output) Push-pull Toggling No
GPIO_6
(primary function)		 VIO (VIO_IN) Input(1) or output PPU/PPD(1) No Push-pull Low or high No
GPIO_6
secondary function:
SYSEN2 		Output N/A (output) N/A (output) High
GPIO_7
(primary function)		 VRTC, fail-safe
(5.25-V tolerance)		 Input(1) or output PPD(1) Yes Open-drain Low or high No
GPIO_7
secondary function:
POWERHOLD 		Input PD fixed No N/A (input) High
NSLEEP VRTC Input PPU(1) or PPD No N/A (input) Low(1) or high No but software possible
ENABLE1 VIO (VIO_IN) Input PPU or PPD(1) No N/A (input) Low or high(1) No but software possible
REGEN1 VSYS (VCC1) Output N/A (output) N/A (output) Push-pull or open- drain (OTP selection) High No
RESET_IN VRTC, fail-safe
(5.25-V tolerance)		 Input PPD(1) Yes N/A (input) Low(1) or high Yes
RESET_OUT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Low No
NRESWARM VRTC Input PPU(1) No N/A (input) Low No
INT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull(1) or open- drain Low(1) or high No but software possible
CLK32KGO VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Toggling No
I2C1_SDA_SDI VIO (VIO_IN) Input or output No No Open-drain High (I2C) Yes (I2C/SPI)
I2C1_SCL_SCK VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI)
I2C2_SCL_SCE VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI)
I2C2_SDA_SD0 VIO (VIO_IN) Input or output No No Open-drain (I2C) or Push-pull (SPI) High (I2C) Yes (I2C/SPI)
GPADC_IN0 VRTC Input No No N/A (analog) Analog No
GPADC_IN1 VANA Input No No N/A (analog) Analog No
GPADC_IN2 VANA Input No No N/A (analog) Analog No
GPADC_VREF VANA Output No No N/A (analog) Analog No
OSC16MIN VRTC Input No No N/A (analog) Analog No
OSC16MOUT VRTC Output No No N/A (analog) Analog No
VCC_SENSE2 VSYS (VCC1) Input No No N/A (analog) Analog No
VCC_SENSE VSYS (VCC1) Input No No N/A (analog) Analog No
(1) Default option.
(2) The pullup and pulldown resistors are defined as follows:
    PUpullup
    PDpulldown
    PPUsoftware-programmable pullup
    PPDsoftware-programmable pulldown