JAJSEF7G December   2014  – February 2019 TPS659037

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
    1.     Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Latch Up Rating
    6. 4.6  Electrical Characteristics: LDO Regulator
    7. 4.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 4.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 4.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 4.11 Electrical Characteristics: DC-DC Clock Sync
    12. 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 4.14 Electrical Characteristics: System Control Threshold
    15. 4.15 Electrical Characteristics: Current Consumption
    16. 4.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 4.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 4.18 Electrical Characteristics: I/O Pullup and Pulldown
    19. 4.19 I2C Interface Timing Requirements
    20. 4.20 SPI Timing Requirements
    21. 4.21 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Power Management
      2. 5.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 5.3.2.1 Step-Down Regulators
          1. 5.3.2.1.1 Sync Clock Functionality
          2. 5.3.2.1.2 Output Voltage and Mode Selection
          3. 5.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 5.3.2.1.4 POWERGOOD
          5. 5.3.2.1.5 DVS-Capable Regulators
          6. 5.3.2.1.6 Non DVS-Capable Regulators
          7. 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 5.3.2.2 LDOs – Low Dropout Regulators
          1. 5.3.2.2.1 LDOVANA
          2. 5.3.2.2.2 LDOVRTC
          3. 5.3.2.2.3 LDO Bypass (LDO9)
          4. 5.3.2.2.4 LDOUSB
          5. 5.3.2.2.5 Other LDOs
      3. 5.3.3  Long-Press Key Detection
      4. 5.3.4  RTC
        1. 5.3.4.1 General Description
        2. 5.3.4.2 Time Calendar Registers
          1. 5.3.4.2.1 TC Registers Read Access
          2. 5.3.4.2.2 TC Registers Write Access
        3. 5.3.4.3 RTC Alarm
        4. 5.3.4.4 RTC Interrupts
        5. 5.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 5.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 5.3.5.1 Asynchronous Conversion Request (SW)
        2. 5.3.5.2 Periodic Conversion Request (AUTO)
        3. 5.3.5.3 Calibration
      6. 5.3.6  General-Purpose I/Os (GPIO Pins)
        1. 5.3.6.1 REGEN Output
      7. 5.3.7  Thermal Monitoring
        1. 5.3.7.1 Hot-Die Function (HD)
        2. 5.3.7.2 Thermal Shutdown (TS)
        3. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 5.3.8  Interrupts
      9. 5.3.9  Control Interfaces
        1. 5.3.9.1 I2C Interfaces
          1. 5.3.9.1.1 I2C Implementation
          2. 5.3.9.1.2 F/S Mode Protocol
          3. 5.3.9.1.3 HS Mode Protocol
        2. 5.3.9.2 Serial-Peripheral Interface (SPI)
          1. 5.3.9.2.1 SPI Modes
          2. 5.3.9.2.2 SPI Protocol
      10. 5.3.10 Device Identification
    4. 5.4 Device Functional Modes
      1. 5.4.1  Embedded Power Controller
      2. 5.4.2  State Transition Requests
        1. 5.4.2.1 ON Requests
        2. 5.4.2.2 OFF Requests
        3. 5.4.2.3 SLEEP and WAKE Requests
      3. 5.4.3  Power Sequences
      4. 5.4.4  Startup Timing and RESET_OUT Generation
      5. 5.4.5  Power On Acknowledge
        1. 5.4.5.1 POWERHOLD Mode
        2. 5.4.5.2 AUTODEVON Mode
      6. 5.4.6  BOOT Configuration
        1. 5.4.6.1 Boot Pin Selection
      7. 5.4.7  Reset Levels
      8. 5.4.8  Warm Reset
      9. 5.4.9  RESET_IN
      10. 5.4.10 Watchdog Timer (WDT)
      11. 5.4.11 System Voltage Monitoring
        1. 5.4.11.1 Generating a POR
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1  Recommended External Components
        2. 6.2.2.2  SMPS Input Capacitors
        3. 6.2.2.3  SMPS Output Capacitors
        4. 6.2.2.4  SMPS Inductors
        5. 6.2.2.5  LDO Input Capacitors
        6. 6.2.2.6  LDO Output Capacitors
        7. 6.2.2.7  VCC1
          1. 6.2.2.7.1 Meeting the Power Down Sequence
          2. 6.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 6.2.2.8  VIO_IN
        9. 6.2.2.9  16-MHz Crystal
        10. 6.2.2.10 GPADC
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 デバイス・サポート
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 ドキュメントのサポート
      1. 9.2.1 関連資料
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 Community Resources
    5. 9.5 商標
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4.2.3 SLEEP and WAKE Requests

SLEEP requests are used to put the TPS659037 device in the SLEEP state, meaning a transition from the ACTIVE to SLEEP state. This sets internal resources into low-power mode, as well as user-defined resources into their user predefined low-power mode. The states of the resources during active and sleep modes are defined in the LDO*_CTRL registers and SMPSx_CTRL registers.

Table 5-12 lists the SLEEP requests. Any of these events trigger the ACT2SLP sequence unless pending interrupts (unmasked) occur. Only an interrupt or NSLEEP inactive (high) generates a WAKE request to wake up the TPS659037 device (exit from the SLEEP state). A WAKE request (only during the SLEEP state) wakes up the device and triggers a SLEEP2ACT or a SLEEP2OFF power sequence.

Table 5-12 SLEEP Requests

EVENT MASKABLE POLARITY COMMENT
NSLEEP (pin) Yes (Default: Masked) Low Level sensitive

For each resource, a transition from the ACTIVE to SLEEP state or SLEEP to ACTIVE state can be controlled in two different ways:

  • Through EPC sequencing (ACT2SLP or SLP2ACT power sequence), when the resource is associated to the NSLEEP signal.
  • Through direct control of the resource power mode (active or sleep).
    • The user can bypass SLEEP and WAKE sequencing by having resources assigned to one external control signal (ENABLE1). This signal has direct control on the power modes (active or sleep) of any resources associated to it and it triggers an immediate switch from one mode to the other, regardless of the EPC sequencing.

All resources can therefore be associated to two external pins (NSLEEP and ENABLE1) and they switch between the SLEEP and ACTIVE states based on Table 5-13.

Table 5-13 Resources SLEEP and ACTIVE Assignments

ENABLE1 ASSIGNMENT NSLEEP ASSIGNMENT ENABLE1 PIN STATE NSLEEP PIN STATE STATE TRANSITION
0 0 Don't care Don't care ACTIVE None
0 1 Don't care 0 ↔ 1 SLEEP ↔ ACTIVE Sequenced
1 0 0 ↔ 1 Don't care SLEEP ↔ ACTIVE Immediate
1 1 0 0 ↔ 1 SLEEP ↔ ACTIVE Sequenced
1 0 ↔ 1 ACTIVE None
0 ↔ 1 0 SLEEP ↔ ACTIVE Immediate
0 ↔ 1 1 ACTIVE None

NOTE

  • The polarity of the NSLEEP and ENABLE1 signals is configurable through the POLARITY_CTRL register. By default:
    • ENABLE1 is active high; a transition from 0 to 1 requests a transition from SLEEP to ACTIVE.
    • NSLEEP is active low; a transition from 1 to 0 requests a transition from ACTIVE to SLEEP.
  • Resource assignments to the NSLEEP and ENABLE1 signals are configured in the ENABLEx_YYY_ASSIGN and NSLEEP_YYY_ASSIGN registers (where x = 1 or 2 and YYY = RES or SMPS or LDO)
  • Several resources can be assigned to the same ENABLE1 signal and therefore, when triggered, they all switch their power mode at the same time.
  • When resources are assigned only to the NSLEEP signal, their respective switching order is controlled and defined in the power sequence.
  • When a resource is not assigned to any signal (NSLEEP and ENABLE1), it never switches from the ACTIVE to SLEEP state. The resource always remains in active mode.

CAUTION

A defect in the digital controller of the TPS659037 device was discovered, which may cause the PLL to shut down unexpectedly under the following sequence of events:

  • PLL is programmed to be OFF under SLEEP mode through the PLLEN_CTRL register
  • NSLEEP is assigned to control the entering of SLEEP mode for the PLL through the NSLEEP_RES_ASSIGN register
  • The TPS659037 device goes through a SLP2OFF state transition followed by an OFF2ACT state transition
  • PLL is again assigned to be OFF in SLEEP mode through the programming of the PLLEN_CTRL and the NSLEEP_RES_ASSIGN registers while the TPS659037 device remains in ACTIVE mode

Two possible actions are recommended to help prevent the PLL from shutting down unexpectedly:

  • [Hardware Implementation] Toggle the NSLEEP pin twice to force the ACT2SLP and SLP2ACT state transitions as soon as the TPS659037 device wakes up from back to back SLP2OFF and OFF2ACT state transitions
  • [Software Implementation] Toggle the NSLEEP_POLARITY bit (0 → 1 → 0) of the POLARITY_CTRL register to force the ACT2SLP and SLP2ACT device state transitions as soon as the TPS659037 device wakes up from back to back SLP2OFF and OFF2ACT state transitions