JAJSEF6L August   2013  – February 2019 TPS659038-Q1 , TPS659039-Q1

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Device Comparison
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
      1.      Pin Functions
    2. 4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch
    3. 4.3 Signal Descriptions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Latch Up Rating
    6. 5.6  Electrical Characteristics: LDO Regulator
    7. 5.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 5.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 5.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 5.11 Electrical Characteristics: DC-DC Clock Sync
    12. 5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 5.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 5.14 Electrical Characteristics: System Control Thresholds
    15. 5.15 Electrical Characteristics: Current Consumption
    16. 5.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 5.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance
    19. 5.19 I2C Interface Timing Requirements
    20. 5.20 SPI Timing Requirements
    21. 5.21 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1  Power Management
      2. 6.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 6.3.2.1 Step-Down Regulators
          1. 6.3.2.1.1 Sync Clock Functionality
          2. 6.3.2.1.2 Output Voltage and Mode Selection
          3. 6.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 6.3.2.1.4 POWERGOOD
          5. 6.3.2.1.5 DVS-Capable Regulators
          6. 6.3.2.1.6 Non DVS-Capable Regulators
          7. 6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 6.3.2.2 LDOs – Low Dropout Regulators
          1. 6.3.2.2.1 LDOVANA
          2. 6.3.2.2.2 LDOVRTC
          3. 6.3.2.2.3 LDO Bypass (LDO9)
          4. 6.3.2.2.4 LDOUSB
          5. 6.3.2.2.5 Other LDOs
      3. 6.3.3  Long-Press Key Detection
      4. 6.3.4  RTC
        1. 6.3.4.1 General Description
        2. 6.3.4.2 Time Calendar Registers
          1. 6.3.4.2.1 TC Registers Read Access
          2. 6.3.4.2.2 TC Registers Write Access
        3. 6.3.4.3 RTC Alarm
        4. 6.3.4.4 RTC Interrupts
        5. 6.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 6.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 6.3.5.1 Asynchronous Conversion Request (SW)
        2. 6.3.5.2 Periodic Conversion Request (AUTO)
        3. 6.3.5.3 Calibration
      6. 6.3.6  General-Purpose I/Os (GPIO Terminals)
        1. 6.3.6.1 REGEN Output
      7. 6.3.7  Thermal Monitoring
        1. 6.3.7.1 Hot-Die Function (HD)
        2. 6.3.7.2 Thermal Shutdown (TS)
        3. 6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 6.3.8  Interrupts
      9. 6.3.9  Control Interfaces
        1. 6.3.9.1 I2C Interfaces
          1. 6.3.9.1.1 I2C Implementation
          2. 6.3.9.1.2 F/S Mode Protocol
          3. 6.3.9.1.3 HS Mode Protocol
        2. 6.3.9.2 SPI Interface
          1. 6.3.9.2.1 SPI Modes
          2. 6.3.9.2.2 SPI Protocol
      10. 6.3.10 Device Identification
    4. 6.4 Device Functional Modes
      1. 6.4.1  Embedded Power Controller
      2. 6.4.2  State Transition Requests
        1. 6.4.2.1 ON Requests
        2. 6.4.2.2 OFF Requests
        3. 6.4.2.3 SLEEP and WAKE Requests
      3. 6.4.3  Power Sequences
      4. 6.4.4  Start Up Timing and RESET_OUT Generation
      5. 6.4.5  Power On Acknowledge
        1. 6.4.5.1 POWERHOLD Mode
        2. 6.4.5.2 AUTODEVON Mode
      6. 6.4.6  BOOT Configuration
        1. 6.4.6.1 Boot Terminal Selection
      7. 6.4.7  Reset Levels
      8. 6.4.8  Warm Reset
      9. 6.4.9  RESET_IN
      10. 6.4.10 Watchdog Timer (WDT)
      11. 6.4.11 System Voltage Monitoring
        1. 6.4.11.1 Generating a POR
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Recommended External Components
        2. 7.2.2.2  SMPS Input Capacitors
        3. 7.2.2.3  SMPS Output Capacitors
        4. 7.2.2.4  SMPS Inductors
        5. 7.2.2.5  LDO Input Capacitors
        6. 7.2.2.6  LDO Output Capacitors
        7. 7.2.2.7  VCC1
          1. 7.2.2.7.1 Meeting the Power Down Sequence
          2. 7.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 7.2.2.8  VIO_IN
        9. 7.2.2.9  16-MHz Crystal
        10. 7.2.2.10 GPADC
      3. 7.2.3 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 デバイスの項目表記
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 関連リンク
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 Community Resources
    6. 10.6 商標
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 パッケージ・マテリアル情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWS|169
サーマルパッド・メカニカル・データ
発注情報

6.3.2.1.3 Current Monitoring and Short Circuit Detection

The step-down converters include several other features.

The SMPS sink current limitation is controlled with the SMPS_NEGATIVE_CURRENT_LIMIT_EN register. The limitation is enabled by default.

Channel 11 of the GPADC can be used to monitor the output current of SMPS12, SMPS3, SMPS123, SMPS45, SMPS457, SMPS6, or SMPS7. Load current monitoring is enabled for a given SMPS in the SMPS_ILMONITOR_EN register. SMPS output power monitoring is intended to be used during the steady state of the output voltage, and is supported in PWM mode only.

Use Equation 1 as the basic equation for the SMPS output current result.

Equation 1. TPS659038-Q1 TPS659039-Q1 EQ_3.gif

where

  • IFS = IFS0 × K (K is the number of active SMPS phases)
  • IOS = IOS0 × K (K is the number of active SMPS phases)

Use Equation 2 to calculate the temperature compensated result.

Equation 2. TPS659038-Q1 TPS659039-Q1 EQ_4.gif

For values of IFS0 and IOS0, see Section 5.12.

The SMPS thermal monitoring is enabled (default) and disabled with the SMPS_THERMAL_EN register. When enabled, the SMPS thermal status is available in the SMPS_THERMAL_STATUS register. SMPS12 and SMPS3 have shared thermal protection, in effect, if SMSP12 triggers the thermal protection, then SMPS3 operating in stand-alone mode is disabled. There is no dedicated thermal protection in SMPS8 or SMPS9.

Each SMPS has a detection for load current above ILIM, indicating overcurrent or shorted SMPS output. A register SMPS_SHORT_STATUS indicates any SMPS short condition. Depending on the interrupt short line mask bit register (INT2_MASK.SHORT), an interrupt is generated upon any shorted SMPS. If a short situation occurs on any enabled SMPSs, the corresponding short status bit is set in the SMPS_SHORT_STATUS register. A switch-off signal is then sent to the corresponding SMPS, and the SMPS remains off until the corresponding bit in the SMPS_SHORT_STATUS register is cleared. The SMPS_SHORT_STATUS register is cleared when read, or by issuing a POR. The same behavior applies to LDO shorts using the LDO_SHORT_STATUS registers.

A short must occur on any enabled SMPS or LDO for at least 155 us to 185 us for the short detection to shut off the rail. During startup of the device, there is a 2 ms counter that masks any short-circuit shutdown. This counter starts when the device is enabled and the counter is reset when any SMPSx or LDOx rail becomes ACTIVE. When no rail has been enabled for 2 ms, the counter reaches its threshold and the short-circuit shutdown is no longer masked for the enabled SMPSs and LDOs.