JAJSEF6L August   2013  – February 2019 TPS659038-Q1 , TPS659039-Q1

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Device Comparison
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
      1.      Pin Functions
    2. 4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch
    3. 4.3 Signal Descriptions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Latch Up Rating
    6. 5.6  Electrical Characteristics: LDO Regulator
    7. 5.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 5.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 5.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 5.11 Electrical Characteristics: DC-DC Clock Sync
    12. 5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 5.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 5.14 Electrical Characteristics: System Control Thresholds
    15. 5.15 Electrical Characteristics: Current Consumption
    16. 5.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 5.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance
    19. 5.19 I2C Interface Timing Requirements
    20. 5.20 SPI Timing Requirements
    21. 5.21 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1  Power Management
      2. 6.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 6.3.2.1 Step-Down Regulators
          1. 6.3.2.1.1 Sync Clock Functionality
          2. 6.3.2.1.2 Output Voltage and Mode Selection
          3. 6.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 6.3.2.1.4 POWERGOOD
          5. 6.3.2.1.5 DVS-Capable Regulators
          6. 6.3.2.1.6 Non DVS-Capable Regulators
          7. 6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 6.3.2.2 LDOs – Low Dropout Regulators
          1. 6.3.2.2.1 LDOVANA
          2. 6.3.2.2.2 LDOVRTC
          3. 6.3.2.2.3 LDO Bypass (LDO9)
          4. 6.3.2.2.4 LDOUSB
          5. 6.3.2.2.5 Other LDOs
      3. 6.3.3  Long-Press Key Detection
      4. 6.3.4  RTC
        1. 6.3.4.1 General Description
        2. 6.3.4.2 Time Calendar Registers
          1. 6.3.4.2.1 TC Registers Read Access
          2. 6.3.4.2.2 TC Registers Write Access
        3. 6.3.4.3 RTC Alarm
        4. 6.3.4.4 RTC Interrupts
        5. 6.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 6.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 6.3.5.1 Asynchronous Conversion Request (SW)
        2. 6.3.5.2 Periodic Conversion Request (AUTO)
        3. 6.3.5.3 Calibration
      6. 6.3.6  General-Purpose I/Os (GPIO Terminals)
        1. 6.3.6.1 REGEN Output
      7. 6.3.7  Thermal Monitoring
        1. 6.3.7.1 Hot-Die Function (HD)
        2. 6.3.7.2 Thermal Shutdown (TS)
        3. 6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 6.3.8  Interrupts
      9. 6.3.9  Control Interfaces
        1. 6.3.9.1 I2C Interfaces
          1. 6.3.9.1.1 I2C Implementation
          2. 6.3.9.1.2 F/S Mode Protocol
          3. 6.3.9.1.3 HS Mode Protocol
        2. 6.3.9.2 SPI Interface
          1. 6.3.9.2.1 SPI Modes
          2. 6.3.9.2.2 SPI Protocol
      10. 6.3.10 Device Identification
    4. 6.4 Device Functional Modes
      1. 6.4.1  Embedded Power Controller
      2. 6.4.2  State Transition Requests
        1. 6.4.2.1 ON Requests
        2. 6.4.2.2 OFF Requests
        3. 6.4.2.3 SLEEP and WAKE Requests
      3. 6.4.3  Power Sequences
      4. 6.4.4  Start Up Timing and RESET_OUT Generation
      5. 6.4.5  Power On Acknowledge
        1. 6.4.5.1 POWERHOLD Mode
        2. 6.4.5.2 AUTODEVON Mode
      6. 6.4.6  BOOT Configuration
        1. 6.4.6.1 Boot Terminal Selection
      7. 6.4.7  Reset Levels
      8. 6.4.8  Warm Reset
      9. 6.4.9  RESET_IN
      10. 6.4.10 Watchdog Timer (WDT)
      11. 6.4.11 System Voltage Monitoring
        1. 6.4.11.1 Generating a POR
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Recommended External Components
        2. 7.2.2.2  SMPS Input Capacitors
        3. 7.2.2.3  SMPS Output Capacitors
        4. 7.2.2.4  SMPS Inductors
        5. 7.2.2.5  LDO Input Capacitors
        6. 7.2.2.6  LDO Output Capacitors
        7. 7.2.2.7  VCC1
          1. 7.2.2.7.1 Meeting the Power Down Sequence
          2. 7.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 7.2.2.8  VIO_IN
        9. 7.2.2.9  16-MHz Crystal
        10. 7.2.2.10 GPADC
      3. 7.2.3 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 デバイスの項目表記
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 関連リンク
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 Community Resources
    6. 10.6 商標
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 パッケージ・マテリアル情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWS|169
サーマルパッド・メカニカル・データ
発注情報

6.3.5 GPADC – 12-Bit Sigma-Delta ADC

The GPADC consists of a 12-bit sigma-delta ADC combined with an analog input multiplexer. The GPADC allows the host processor to monitor a variety of analog signals using analog-to-digital conversion on the input source. After the conversion completes, an interrupt is generated for the host processor and it can read the result of the conversion through the I2C interface.

The GPADC on this PMIC supports 16 analog inputs. However only a total of 9 inputs are available for the application use. Three of these inputs are available on external balls, and the remaining six are dedicated to internal resource monitoring. One of the three external inputs is associated with a current source allowing measurements of resistive elements (thermal sensor). To improve the measurement accuracy, the reference voltages GPADC_VREF can be used with an external resistor for the NTC resistor measurement. The reference voltage GPADC_VREF is always present when the GPADC is enabled.

GPADC_IN0 is associated with three selectable current sources. The selectable current levels are 5, 15, and 20 μA.

GPADC_IN1 is intended to measure temperature with an NTC sensor connected to ground. Two resistors, one in parallel with the NTC resistor and the other one between GPADC_IN1 and GPADC_VREF, can be used to modify the exponential function of the NTC resistor.

Figure 6-9 shows the block diagram of the GPADC.

TPS659038-Q1 TPS659039-Q1 Block_Diagram_of_the_GPADC_SWCS095.gifFigure 6-9 Block Diagram of the GPADC

For all the measurements performed by the monitoring GPADC, voltage dividers, current to voltage converters, and current source are integrated in the TPS65903x-Q1 devices to scale the signal to be measured to the GPADC input range.

The conversion requests are initiated by the host processor either by software through the I2C. This mode is useful when real-time conversion is required.

There are two kinds of conversion requests with the following priority:

  • Asynchronous conversion request (SW)
  • Periodic conversion (AUTO)

The EXTEND_DELAY bit in the GPADC_RT_CTRL register can extend by 400 μs the delay from the channel selection or triggering to the sampling.

Use Equation 3 to convert from the GPADC code to the internal die temperature using GPADC channels 12 and 13.

Equation 3. TPS659038-Q1 TPS659039-Q1 tps65903x-q1-die-temperature-equation.gif

Table 6-3 GPADC Channel Assignments

CHANNEL TYPE INPUT VOLTAGE FULL RANGE(1) INPUT VOLTAGE PERFORMANCE RANGE(2) SCALER OPERATION
0 (GPADC_IN0) External(3) 0 to 1.25 V 0.01 to 1.215 V No Resistor value or general purpose. Select source current 0, 5, 15, or 20 μA
1 (GPADC_IN1) External(3) 0 to 1.25 V 0.01 to 1.215 V No Platform temperature, NTC resistor value and general purpose
2 (GPADC_IN2) External(3) 0 to 2.5 V 0.02 to 2.43 V 2 Audio accessory or general purpose
7 (VCC_SENSE) Internal 2.5 to 5 V when HIGH_VCC_SENSE = 0
2.3 V to (VCC1–1 V) when HIGH_VCC_SENSE = 1		 2.5 to 4.86 V when HIGH_VCC_SENSE = 0
2.3 V to (VCC1–1 V) when HIGH_VCC_SENSE = 1		 4 System supply voltage (VCC_SENSE)
10 (VBUS) Internal 0 to 6.875V 0.055 to 5.25V 5,5 VBUS Voltage
11 Internal 0 to 1.25 V No DC-DC current probe
12 Internal 0 to 1.25 V 0 to 1.215 V No PMIC internal die temperature
13 Internal 0 to 1.25 V 0 to 1.215 V No PMIC internal die temperature
15 Internal 0 to VCC1 V 0.055 to VCC1 V 5 Test network
(1) The minimum and maximum voltage full range corresponds to typical minimum and maximum output codes (0 and 4095).
(2) The performance voltage is a range where gain error drift, offset drift, INL and DNL parameters are specified.
(3) If VANA LDO is OFF, maximum current to draw from GPADC_INx is 1 mA for reliability. For current higher than 1-mA VANA must be set to SLEEP or ACTIVE mode.