JAJSDU8C March   2016  – February 2019 TPS65916

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, SMPS4, and SMPS5
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.5 Electrical Characteristics — LDO Regulators

Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input filtering capacitance (C18, C19) Connected from LDOx_IN to GND
Shared input tank capacitance (depending on platform requirements)		 0.6 2.2 µF
Output filtering capacitance (C20, C21, C22, C23, C24)(2) Connected from LDOx_OUT to GND 0.6 2.2 2.7 µF
CESR Filtering capacitor ESR < 100 kHz 20 100 600 mΩ
1 to 10 MHz 1 10 20
VIN(LDOx) Input voltage LDO1, LDO2 from LDO12_IN, Normal Mode 0.9 V ≤ VOUT < 2.2 V 1.2 VCCA V
2.2 V ≤ VOUT ≤ 3.3 V 1.2 5.25
LDO1, LDO2 from LDO12_IN, Bypass Mode VOUT = VIN 1.2 3.6
LDO3, LDO4, LDO5 from LDO3_IN, LDO4_IN and LDO5_IN 0.9 V ≤ VOUT < 2.2 V 1.75 VCCA
2.2 V ≤ VOUT ≤ 3.3 V 1.75 5.25
VOUT(LDOx) LDO output voltage programmable(1) (except LDOVRTC and LDOVANA) Range 0.9 3.3 V
Step size 50 mV
TDCOV(LDOx) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature All LDOs except LDOVANA and LDOVRTC
VIN(LDOx) ≥ 2.5 V		 0.99 × VOUT(LDOx) – 0.014 1.006 × VOUT(LDOx) + 0.014 V
All LDOs except LDOVANA and LDOVRTC
VIN(LDOx) < 2.5 V and VOUT(LDOx) < 1.5 V		 0.99 × VOUT(LDOx) – 0.014 1.006 × VOUT(LDOx) + 0.014
TDCOV(LDOx) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature LDOVRTC_OUT –40°C ≤ TA ≤ 85°C 1.726 1.8 1.85 V
85°C <TA ≤ 105°C 1.726 1.8 1.85
TDCOV(LDOx) Total DC output voltage accuracy, including voltage references, DC load and line regulations, process and temperature LDOVANA_OUT –40°C ≤ TA ≤ 85°C 2.002 2.093 2.14 V
85°C <TA ≤ 105°C 2.002 2.093 2.14
DV(LDOx) Dropout voltage
DV(LDOx)= VIN – VOUT
where
VOUT = VOUTnom – 2%		 LDO1, LDO2: IOUT = IOUTmax 150 mV
LDO3, LDO4: IOUT = IOUTmax 290
LDO5: IOUT = 50 mA 150
LDO5: IOUT = IOUTmax (not low-noise performance) 290
IOUT(LDOx) Output current LDO1, LDO2 300 mA
LDO3, LDO4 200
LDO5 100
IOUT(LDOx) Output current, internal LDOs LDOVANA in Active Mode 10 mA
IOUT(LDOx) Output current, internal LDOs LDOVRTC in Active Mode 25 mA
ISHORT(LDOx) LDO current limitation LDO1, LDO2 380 600 1800 mA
LDO3, LDO4 340 650 1300
LDO5 135 325 740
LDO inrush current LDO1, LDO2 500 mA
DCLDR DC load regulation, ΔVOUT IOUT = 0 to IOUTmax at pin, LDO1, LDO2 –40°C ≤ TA ≤ 85°C 4 16 mV
85°C <TA ≤ 105°C 4 16
IOUT = 0 to IOUTmax at pin, all other LDOs –40°C ≤ TA ≤ 85°C 4 14
85°C <TA ≤ 105°C 4 14
DCLNR DC line regulation, ΔVOUT / VOUT VIN = VINmin to VINmax, IOUT = IOUTmax –40°C ≤ TA ≤ 85°C 0.1% 0.2%
85°C <TA ≤ 105°C 0.1% 0.2%
VSYS = VSYSmin to VSYSmax, IOUT = IOUTmax. VINconstant (LDO preregulated), VOUT ≤ 2.2 V –40°C ≤ TA ≤ 85°C 0.3% 0.75%
85°C <TA ≤ 105°C 0.3% 0.75%
RDIS Pulldown discharge resistance at LDO output, except LDOVRTC Off mode, pulldown enabled and LDO disabled. Applies to bypass mode also. 30 125 Ω
Power supply ripple rejection (PSRR), LDO1, LDO2 f = 217 Hz, IOUT = IOUTmax 55 90 dB
f = 50 kHz, IOUT = IOUTmax 35 45
f = 1 MHz, IOUT = IOUTmax 25 35
Power supply ripple rejection (PSRR), LDO3, LDO4 f = 217 Hz, IOUT = IOUTmax 55 90
f = 50 kHz, IOUT = IOUTmax 25 45
f = 1 MHz, IOUT = IOUTmax 20 35
Power supply ripple rejection (PSRR), LDO5 f = 217 Hz, IOUT = IOUTmax 55 90
f = 50 kHz, IOUT = IOUTmax 25 45
f = 1 MHz, IOUT = IOUTmax 25 35
IQoff Quiescent current – off mode For all LDOs, VCCA = VIN(LDOx) = 3.8 V, TA = 27°C 0.1 0.4 µA
For all LDOs, VCCA = VIN(LDOx) = 3.8 V, TA = 85°C 0.2 1.3
For all LDOs, VCCA = VIN(LDOx) = 3.8 V, TA = 105°C 0.2 1.3
IQon(LDO) Quiescent current – LDO on mode ILOAD = 0 mA (LDO1, LDO2),
VIN(LDOx) > VOUT(LDOx) + DV(LDOx) 		–40°C ≤ TA ≤ 85°C 46 70 µA
85°C <TA ≤ 105°C 46 70
ILOAD = 0 mA (LDO3, LDO4),
VIN(LDOx) > VOUT(LDOx) + DV(LDOx) 		–40°C ≤ TA ≤ 85°C 36 47
85°C <TA ≤ 105°C 36 47
ILOAD = 0 mA (LDO5) ,
VOUT ≤ 1.8 V, VIN(LDOx) > VOUT(LDOx) + DV(LDOx) 		–40°C ≤ TA ≤ 85°C 140 190
85°C <TA ≤ 105°C 140 190
ILOAD = 0 mA (LDO5) ,
VOUT > 1.8 V, VIN(LDOx) > VOUT(LDOx) + DV(LDOx) 		–40°C ≤ TA ≤ 85°C 180 210
85°C <TA ≤ 105°C 180 210
αQ Quiescent current coefficient
LDO on mode, IQout = IQon + αQ × IOUT 		IOUT < 100 µA 4%
100 µA ≤ IOUT < 1 mA 2%
IOUT ≥ 1 mA 1%
TLDR Transient load regulation, ΔVOUT On mode, IOUT = 10 mA to IOUTmax / 2, TR = TF = 1 µs. All LDOs except LDO5 –25 25 mV
On mode, IOUT = 1 mA to IOUTmax / 2, TR = TF = 1 µs. LDO5 –25 25
On mode, IOUT = 100 µA to IOUTmax / 2, TR = TF = 1 µs –50 33
TLNR Transient line regulation,
ΔVOUT / VOUT 		VIN step = 600 mVpp, TR = TF = 10 µs 0.25% 0.5%
VSYS step = 600 mVpp, TR = TF = 10 µs. VINconstant (LDO preregulated), VOUT ≤ 2.2 V 0.8% 1.6%
Noise (except LDO5) 100 Hz < f ≤ 10 kHz 5000 8000 nV/√Hz
10 kHz < f ≤ 100 kHz 1250 2500
100 kHz < f ≤ 1 MHz 150 300
f > 1 MHz 250 500
Noise (LDO5) 100 Hz < f ≤ 5 kHz, IOUT = 50 mA , VOUT ≤ 1.8 V 400 500 nV/√Hz
5 kHz < f ≤ 400 kHz, IOUT = 50 mA , VOUT ≤ 1.8 V 62 125
400 kHz < f ≤ 10 MHz, IOUT = 50 mA , VOUT ≤ 1.8 V 25 50
Ripple LDO1, LDO2, ripple at 32 kHz (from the internal charge pump of 300 mA LDO) 5 mVPP
LDO BYPASS MODE LDO1, LDO2
Bypass resistance of 300 mA LDO 2.9 V ≤ VIN ≤ 3.3 V, VSYS ≥ 3.4 V, IOUT = 250 mA, programmed to BYPASS 0.22 Ω
Bypass resistance of 300 mA LDO 1.75 V ≤ VIN ≤ 1.9 V, IOUT = 75 mA , programmed to BYPASS 0.24 Ω
Bypass resistance of 300 mA LDO 1.75 V ≤ VIN ≤ 1.9 V, IOUT = 200 mA , programmed to BYPASS 0.24 Ω
Bypass mode inrush current Maximum 50 µF load connected to LDOx_OUT 1100 mA
IQon(bypass) Quiescent current – bypass mode 60 µA
Slew-rate 60 mV/µs
(1) LDO output voltages are programmed separately.
(2) Additional information about how this parameter is specified is located in Section 6.2.2.