JAJSDU8C March   2016  – February 2019 TPS65916

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, SMPS4, and SMPS5
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3.2 Signal Descriptions

Table 3-1 Signal Descriptions

SIGNAL NAME LEVEL I/O(1) INPUT PU/PD(2) PU/PD SELECTION OUTPUT TYPE SELECTION ACTIVITY OTP POLARITY SELECTION
PWRON VSYS (VCCA) Input PU fixed N/A (fixed) N/A (input) Low No
BOOT VRTC Tri-level input N/A (input) N/A (input) N/A (input) Boot conf. No
GPIO_0
(primary function)		 VRTC, fail-safe (5.25-V tolerance) Input(1)/output PPD OTP/SW Open-drain Low or high Yes
GPIO_0
secondary function: PWRDOWN		 Input PPD (Opt. Ext. PU) OTP/SW N/A (input) High Yes
GPIO_0
secondary function: ENABLE2		 Input PPD(1) SW N/A (input) High No, but software possible
GPIO_0
secondary function: REGEN1(3) 		Output N/A (output) N/A (output) Open-drain High No
GPIO_1
(primary function)		 VRTC, fail-safe (5.25-V tolerance) Input(1)/output PPD OTP/SW Open-drain Low or high Yes
GPIO_1
secondary function: RESET_IN		 Input PPD OTP/SW N/A (input) Low Yes
GPIO_1
secondary function: NRESWARM		 Input PPD OTP/SW N/A (input) Low or high Yes
GPIO_1
secondary function: VBUS_SENSE		 Input No No N/A (input) High No
GPIO_2
(primary function)		 VIO (VIO_IN) Input(1)/output PPU/PPD OTP/SW Push-pull(1) or open-drain Low or high Yes
GPIO_2
secondary function: ENABLE1		 Input PPU/PPD(1) SW N/A (input) High No, but software possible
GPIO_2
secondary function: I2C2_SDA_SDO 		Input/output No No Open-drain High No
GPIO_3
(primary function)		 VRTC, fail-safe (5.25-V tolerance) Input(1)/output PPD OTP/SW Open-drain Low or high Yes
GPIO_3
secondary function: ENABLE2		 Input PPD(1) SW N/A (input) High No, but software possible
GPIO_3
secondary function: REGEN1(3) 		Output N/A (output) N/A (output) Open-drain High No
GPIO_3
secondary function: SYNCDCDC 		Input PPD(1) SW N/A (input) Toggling No
GPIO_4
(primary function)		 VIO (VIO_IN) Input(1)/output PPU/PPD OTP/SW Push-pull(1) or open-drain Low or high Yes
GPIO_4
secondary function: REGEN2		 Output N/A (output) N/A (output) Push-pull(1) or open-drain High No
GPIO_4
secondary function: I2C2_SCL_SCE		 Input No No N/A (input) High No
GPIO_5
(primary function)		 VRTC, fail-safe (5.25-V tolerance) Input(1)/output PPD OTP/SW Open-drain Low or high Yes
GPIO_5
secondary function: POWERHOLD 		Input PPD(1) SW N/A (input) High Yes
GPIO_5
secondary function: REGEN3(3) 		Output N/A (output) N/A (output) Open-drain High No
GPIO_6
(primary function)		 VRTC Input(1)/output PPD OTP/SW Open-drain Low or high Yes
GPIO_6
secondary function: NSLEEP		 Input PPU(1)/PPD SW N/A (input) Low Yes
GPIO_6
secondary function: POWERGOOD(3) 		Output N/A (output) N/A (output) Open-drain Low or high Yes
GPIO_6
secondary function: REGEN3(3) 		Output N/A (output) N/A (output) Open-drain High No
RESET_OUT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull(1) or open-drain Low No
INT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull(1) or open-drain Low No, but software possible
SYNCCLKOUT VRTC Output N/A (output) N/A (output) Push-pull Toggling No
I2C1_SDA_SDI VIO (VIO_IN) Input/output No No Open-drain High No
I2C1_SCL_CLK VIO (VIO_IN) Input No No N/A (input) High No
VCC_SENSE VSYS (VCCA) Input No No N/A (analog) Analog No
(1) Default option.
(2) Pullup and pulldown resistors: PU = Pullup, PD = Pulldown, PPU = Software-programmable pullup, PPD = Software-programmable pulldown.
(3) This pin should not be pulled up to an always-on voltage domain. Before OTP is loaded, this will be configured as an input, and an active pull-up domain will pull this pin to a high level.