JAJSGV4D July   2015  – February 2019 TPS65917-Q1

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, SMPS4, and SMPS5
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGZ|48
サーマルパッド・メカニカル・データ
発注情報

4.6 Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration

Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input capacitance (C8, C9) 4.7 µF
Output capacitance (C13, C14)(2) SMPS1&2 input dual phase operation, per phase 33 47 57 µF
CESR Filtering capacitor ESR 1 to 10 MHz 2 10 mΩ
Output filter inductance (L1, L2) SMPSx_SW 0.7 1 1.3 µH
DCRL Filter inductor DC resistance 50 100 mΩ
VIN (SMPSx) Input voltage range, SMPSx_IN VSYS (VCCA) 3.135 5.25 V
VOUT (SMPSx) Output voltage, programmable, SMPSx RANGE = 0 (value for RANGE must not be changed when SMPS is active). In ECO mode the output voltage values are fixed (defined before ECO mode is enabled). RANGE = 1 is not supported in Multi-phase configuration. 0.7 1.65 V
Step size, 0.7 V ≤ VOUT ≤ 1.65 V (RANGE = 0) 10 mV
DC output voltage accuracy, includes voltage references, DC load and line regulation, process and temperature ECO mode –3% 4%
PWM mode –1% 2%
Ripple, dual phase Max load, VIN = 3.8 V, VOUT = 1.2 V, ESRCOUT = 2 mΩ, measure with 20-MHz LPF 4 mVPP
DCLNR DC line regulation,
ΔVOUT / VOUT 		VIN = VINmin to VINmax 0.1 %/V
DCLDR DC load regulation,
ΔVOUT / VOUT 		IOUT = 0 to IOUTmax 0.1 %/A
TLDSR Transient load step response, dual phase IOUT = 0.8 to 2 A, TR = TF = 400 ns, COUT = 47 µF , L = 1 µH 3%
IOUT = 0.5 to 500 mA, TR = TF = 100 ns, COUT = 47 µF , L = 1 µH 3%
IOUTmax Rated output current, SMPS1&2 Advance thermal design is required to avoide thermal shut down 7 A
Maximum output current, ECO mode 5 mA
ILIM HS FET High-side MOSFET forward current limit SMPS1&2, each phase 4.2 4.5 A
ILIM LS FET Low-side MOSFET forward current limit SMPS1&2, each phase 4.2 A
RDS(ON) HS FET N-channel MOSFET on-resistance, high-side FET SMPS1&2, each phase 50 mΩ
RDS(ON) LS FET N-channel MOSFET on-resistance, low-side FET SMPS1&2, each phase 39 mΩ
Output voltage slew rate (3) RANGE = 1 2.5 mV/μs
RDIS Pulldown discharge resistance output SMPSx_FDBK, SMPS turned off 375 Ω
SMPSx_SW, SMPS turned off. Pulldown is at master phase output. 9 22
RSENSE Input resistance for remote sense (sense line) Between SMPS1_FDBK and SMPS2_FDBK 260 2200 kΩ
IQoff Quiescent current – Off mode ILOAD = 0 mA 0.1 2.5 μA
IQon(ON) Quiescent current – On mode, dual phase ECO mode, device not switching, –40°C ≤TA ≤ 85°C 15 25 µA
ECO mode, device not switching, 85°C < TA ≤105°C 18 25.5
PWM mode,
ILOAD = 0 mA, VIN = 3.8 V, VOUT = 1 V, device switching, 1-phase operation		 11 mA
VSMPSPG Powergood threshold SMPS1, SMPS2 SMPS output voltage rising, referenced to programmed output voltage –4%
SMPS output voltage falling, referenced to programmed output voltage –16%
IL_AVG_COMP Powergood: GPADC monitoring SMPS1&2 IL_AVG_COMP_rising 6 A
IL_AVG_COMP_falling IL_AVG_COMP_rising-5%
(1) SMPS1 and SMPS2 can be used in parallel in dual-phase mode to be able to multiply the output current by 2, and the converter is named SMPS1&2. The naming SMPS1 and SMPS2 is used when the bucks are configured as a separate buck converters.
(2) Additional information about how this parameter is specified is located inSection 6.2.2.
(3) This slew rate refers to the rate at which the output voltage changes from one voltage level to another voltage after startup is complete.