JAJSGV4D
July 2015 – February 2019
TPS65917-Q1
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
チャネル 1 の機能図
2
改訂履歴
3
Pin Configuration and Functions
3.1
Pin Attributes
Pin Attributes
3.2
Signal Descriptions
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Thermal Information
4.5
Electrical Characteristics — LDO Regulators
4.6
Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
4.7
Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
4.8
Electrical Characteristics — Reference Generator (Bandgap)
4.9
Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
4.10
Electrical Characteristics — 12-Bit Sigma-Delta ADC
4.11
Electrical Characteristics — Thermal Monitoring and Shutdown
4.12
Electrical Characteristics — System Control Thresholds
4.13
Electrical Characteristics — Current Consumption
4.14
Electrical Characteristics — Digital Input Signal Parameters
4.15
Electrical Characteristics — Digital Output Signal Parameters
4.16
I/O Pullup and Pulldown Characteristics
4.17
Electrical Characteristics — I2C Interface
4.18
Timing Requirements — I2C Interface
4.19
Timing Requirements — SPI
4.20
Switching Characteristics — LDO Regulators
4.21
Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
4.22
Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
4.23
Switching Characteristics — Reference Generator (Bandgap)
4.24
Switching Characteristics — PLL for SMPS Clock Generation
4.25
Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
4.26
Switching Characteristics — 12-Bit Sigma-Delta ADC
4.27
Typical Characteristics
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Device State Machine
5.3.1
Embedded Power Controller
5.3.2
State Transition Requests
5.3.2.1
ON Requests
5.3.2.2
OFF Requests
5.3.2.3
SLEEP and WAKE Requests
5.3.3
Power Sequences
5.3.4
Device Power Up Timing
5.3.5
Power-On Acknowledge
5.3.5.1
POWERHOLD Mode
5.3.5.2
AUTODEVON Mode
5.3.6
BOOT Configuration
5.3.6.1
Boot Pin Usage and Connection
5.3.7
Reset Levels
5.3.8
INT
5.3.9
Warm Reset
5.3.10
RESET_IN
5.4
Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
5.4.1
Step-Down Regulators
5.4.1.1
Output Voltage and Mode Selection
5.4.1.2
Clock Generation for SMPS
5.4.1.3
Current Monitoring and Short Circuit Detection
5.4.1.4
POWERGOOD
5.4.1.5
DVS-Capable Regulators
5.4.1.5.1
Non DVS-Capable Regulators
5.4.1.6
Step-Down Converters SMPS1, SMPS2 or SMPS1&2
5.4.1.7
Step-Down Converters SMPS3, SMPS4, and SMPS5
5.4.2
Low Dropout Regulators (LDOs)
5.4.2.1
LDOVANA
5.4.2.2
LDOVRTC
5.4.2.3
LDO1 and LDO2
5.4.2.4
Low-Noise LDO (LDO5)
5.4.2.5
Other LDOs
5.5
SMPS and LDO Input Supply Connections
5.6
First Supply Detection
5.7
Long-Press Key Detection
5.8
12-Bit Sigma-Delta General-Purpose ADC (GPADC)
5.8.1
Asynchronous Conversion Request (SW)
5.8.2
Periodic Conversion (AUTO)
5.8.3
Calibration
5.9
General-Purpose I/Os (GPIO Pins)
5.10
Thermal Monitoring
5.10.1
Hot-Die Function (HD)
5.10.2
Thermal Shutdown
5.11
Interrupts
5.12
Control Interfaces
5.12.1
I2C Interfaces
5.12.1.1
I2C Implementation
5.12.1.2
F/S Mode Protocol
5.12.1.3
HS Mode Protocol
5.12.2
Serial Peripheral Interface (SPI)
5.12.2.1
SPI Modes
5.12.2.2
SPI Protocol
5.13
OTP Configuration Memory
5.14
Watchdog Timer (WDT)
5.15
System Voltage Monitoring
5.16
Register Map
5.16.1
Functional Register Mapping
5.17
Device Identification
6
Applications, Implementation, and Layout
6.1
Application Information
6.2
Typical Application
6.2.1
Design Requirements
6.2.2
Detailed Design Procedure
6.2.2.1
SMPS Input Capacitors
6.2.2.2
SMPS Output Capacitors
6.2.2.3
SMPS Inductors
6.2.2.4
LDO Input Capacitors
6.2.2.5
LDO Output Capacitors
6.2.2.6
VCCA
6.2.2.6.1
Meeting the Power-Down Sequence
6.2.2.6.2
Maintaining Sufficient Input Voltage
6.2.2.7
VIO_IN
6.2.2.8
GPADC
6.2.3
Application Curves
6.3
Layout
6.3.1
Layout Guidelines
6.3.2
Layout Example
6.4
Power Supply Coupling and Bulk Capacitors
7
デバイスおよびドキュメントのサポート
7.1
デバイス・サポート
7.1.1
Third-Party Products Disclaimer
7.1.2
デバイスの項目表記
7.2
ドキュメントのサポート
7.2.1
関連資料
7.3
ドキュメントの更新通知を受け取る方法
7.4
Community Resources
7.5
商標
7.6
静電気放電に関する注意事項
7.7
Glossary
8
メカニカル、パッケージ、および注文情報
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RGZ|48
サーマルパッド・メカニカル・データ
発注情報
jajsgv4d_oa
jajsgv4d_pm
4.17
Electrical Characteristics — I
2
C Interface
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C
B
Capacitive load for SDA and SCL
400
pF