JAJSGV4D July 2015 – February 2019 TPS65917-Q1
PRODUCTION DATA.
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PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSYNC | Synchronization range of SYNCDCDC clock | 1.7 | 2.2 | 2.7 | MHz | |
ADITHER | Dither amplitude of SYNCDCDC clock | 128 | kHz | |||
MDITHER | Dither slope of SYNCDCDC clock | 1.35 | kHz/µs | |||
fFALLBACK | Fallback frequency | VCCA = 5.25 V | 1.98 | 2.2 | 2.42 | MHz |
VCCA = 3.8 V | 1.9 | 2.2 | 2.42 | |||
VCCA = 3.135 V | 1.9 | 2.2 | 2.42 | |||
fSAT,LO | The low saturation frequency of the PLL | 1.35 | 1.68 | MHz | ||
fSAT,HI | The high saturation frequency of the PLL | 2.8 | 3.8 | MHz | ||
tSETTLE | Settling time | Time from initial application or removal of sync clock until PLL output has settled to 1% of the final value | 100 | µs | ||
fERROR | Frequency error | The steady-state percent of difference between fSYNC and the switching frequency | –1% | 1% |