JAJSGV4D July   2015  – February 2019 TPS65917-Q1

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 チャネル 1 の機能図
  2. 2改訂履歴
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Attributes
      1.      Pin Attributes
    2. 3.2 Signal Descriptions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics — LDO Regulators
    6. 4.6  Electrical Characteristics — SMPS1&2 in Dual-Phase Configuration
    7. 4.7  Electrical Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    8. 4.8  Electrical Characteristics — Reference Generator (Bandgap)
    9. 4.9  Electrical Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    10. 4.10 Electrical Characteristics — 12-Bit Sigma-Delta ADC
    11. 4.11 Electrical Characteristics — Thermal Monitoring and Shutdown
    12. 4.12 Electrical Characteristics — System Control Thresholds
    13. 4.13 Electrical Characteristics — Current Consumption
    14. 4.14 Electrical Characteristics — Digital Input Signal Parameters
    15. 4.15 Electrical Characteristics — Digital Output Signal Parameters
    16. 4.16 I/O Pullup and Pulldown Characteristics
    17. 4.17 Electrical Characteristics — I2C Interface
    18. 4.18 Timing Requirements — I2C Interface
    19. 4.19 Timing Requirements — SPI
    20. 4.20 Switching Characteristics — LDO Regulators
    21. 4.21 Switching Characteristics — SMPS1&2 in Dual-Phase Configuration
    22. 4.22 Switching Characteristics — SMPS1, SMPS2, SMPS3, SMPS4, and SMPS5 Stand-Alone Regulators
    23. 4.23 Switching Characteristics — Reference Generator (Bandgap)
    24. 4.24 Switching Characteristics — PLL for SMPS Clock Generation
    25. 4.25 Switching Characteristics — 32-kHz RC Oscillators and SYNCCLKOUT Output Buffers
    26. 4.26 Switching Characteristics — 12-Bit Sigma-Delta ADC
    27. 4.27 Typical Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Device State Machine
      1. 5.3.1  Embedded Power Controller
      2. 5.3.2  State Transition Requests
        1. 5.3.2.1 ON Requests
        2. 5.3.2.2 OFF Requests
        3. 5.3.2.3 SLEEP and WAKE Requests
      3. 5.3.3  Power Sequences
      4. 5.3.4  Device Power Up Timing
      5. 5.3.5  Power-On Acknowledge
        1. 5.3.5.1 POWERHOLD Mode
        2. 5.3.5.2 AUTODEVON Mode
      6. 5.3.6  BOOT Configuration
        1. 5.3.6.1 Boot Pin Usage and Connection
      7. 5.3.7  Reset Levels
      8. 5.3.8  INT
      9. 5.3.9  Warm Reset
      10. 5.3.10 RESET_IN
    4. 5.4  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
      1. 5.4.1 Step-Down Regulators
        1. 5.4.1.1 Output Voltage and Mode Selection
        2. 5.4.1.2 Clock Generation for SMPS
        3. 5.4.1.3 Current Monitoring and Short Circuit Detection
        4. 5.4.1.4 POWERGOOD
        5. 5.4.1.5 DVS-Capable Regulators
          1. 5.4.1.5.1 Non DVS-Capable Regulators
        6. 5.4.1.6 Step-Down Converters SMPS1, SMPS2 or SMPS1&2
        7. 5.4.1.7 Step-Down Converters SMPS3, SMPS4, and SMPS5
      2. 5.4.2 Low Dropout Regulators (LDOs)
        1. 5.4.2.1 LDOVANA
        2. 5.4.2.2 LDOVRTC
        3. 5.4.2.3 LDO1 and LDO2
        4. 5.4.2.4 Low-Noise LDO (LDO5)
        5. 5.4.2.5 Other LDOs
    5. 5.5  SMPS and LDO Input Supply Connections
    6. 5.6  First Supply Detection
    7. 5.7  Long-Press Key Detection
    8. 5.8  12-Bit Sigma-Delta General-Purpose ADC (GPADC)
      1. 5.8.1 Asynchronous Conversion Request (SW)
      2. 5.8.2 Periodic Conversion (AUTO)
      3. 5.8.3 Calibration
    9. 5.9  General-Purpose I/Os (GPIO Pins)
    10. 5.10 Thermal Monitoring
      1. 5.10.1 Hot-Die Function (HD)
      2. 5.10.2 Thermal Shutdown
    11. 5.11 Interrupts
    12. 5.12 Control Interfaces
      1. 5.12.1 I2C Interfaces
        1. 5.12.1.1 I2C Implementation
        2. 5.12.1.2 F/S Mode Protocol
        3. 5.12.1.3 HS Mode Protocol
      2. 5.12.2 Serial Peripheral Interface (SPI)
        1. 5.12.2.1 SPI Modes
        2. 5.12.2.2 SPI Protocol
    13. 5.13 OTP Configuration Memory
    14. 5.14 Watchdog Timer (WDT)
    15. 5.15 System Voltage Monitoring
    16. 5.16 Register Map
      1. 5.16.1 Functional Register Mapping
    17. 5.17 Device Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 SMPS Input Capacitors
        2. 6.2.2.2 SMPS Output Capacitors
        3. 6.2.2.3 SMPS Inductors
        4. 6.2.2.4 LDO Input Capacitors
        5. 6.2.2.5 LDO Output Capacitors
        6. 6.2.2.6 VCCA
          1. 6.2.2.6.1 Meeting the Power-Down Sequence
          2. 6.2.2.6.2 Maintaining Sufficient Input Voltage
        7. 6.2.2.7 VIO_IN
        8. 6.2.2.8 GPADC
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Coupling and Bulk Capacitors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイス・サポート
      1. 7.1.1 Third-Party Products Disclaimer
      2. 7.1.2 デバイスの項目表記
    2. 7.2 ドキュメントのサポート
      1. 7.2.1 関連資料
    3. 7.3 ドキュメントの更新通知を受け取る方法
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGZ|48
サーマルパッド・メカニカル・データ
発注情報

5.9 General-Purpose I/Os (GPIO Pins)

The TPS65917-Q1 device integrates seven configurable general-purpose I/Os that are multiplexed with alternative features as listed in Table 5-11

Table 5-11 General Purpose I/Os Multiplexed Functions

PIN PRIMARY FUNCTION SECONDARY FUNCTION
GPIO_0 General-purpose I/O Port 0 Input: PWRDOWN (Power down signal)
Input: ENABLE2 (Peripheral power request input 2)
Output: REGEN1 (External regulator enable output 4)
GPIO_1 General-purpose I/O Port 1 Input: RESET_IN (Reset input)
Input: NRESWARM (Warm reset input)
Input: VBUS_SENSE (VBUS input)
GPIO_2 General-purpose I/O Port 2 Input: ENABLE1 (Peripheral power request input 1)
Input/Output: I2C2_SDA_SDO (DVS control I2C serial bidirectional data) or SPI output data signal
GPIO_3 General-purpose I/O Port 3 Input: ENABLE2 (Peripheral power request input 2)
Output: REGEN1 (External regulator enable output 1)
Input: SYNCDCDC (SMPS clock synchronization input)
GPIO_4 General-purpose I/O Port 4 Output: REGEN2 (External regulator enable output 2)
Input/Output: I2C2_SCL_SCE (DVS control I2C serial clock) or SPI chip-select signal
GPIO_5 General-purpose I/O Port 5 Input: POWERHOLD (Power hold input)
Output: REGEN3 (External regulator enable output 3)
GPIO_6 General-purpose I/O Port 6 Input: NSLEEP (Sleep mode request signal)
Output: POWERGOOD (Indicator signal for valid regulator output voltages)
Output: REGEN3 (External regulator enable output 3)

For GPIOs characteristics, refer to:

Each GPIO event can generate an interrupt on a rising edge, falling edge, or both; each line is individually maskable (as described in Section 5.11). A GPIO-interrupt applies only when the primary function (general-purpose I/O) has been selected.

All GPIOs can be used as wake-up events.

NOTE

GPIO_2 and GPIO_4 are in the VIO domain (only the I/O supply is required to be available) and therefore these GPIOs cannot be used as ON requests from the OFF mode.

The REGEN1 output is muxed in GPIO_0 and GPIO_3, the REGEN2 output is muxed in GPIO_4, and the REGEN3 output is muxed in GPIO_5 and GPIO_6. When the GPO_0, GPIO_3, GPIO_4, GPIO_5, and GPIO_6 pins are configured as REGEN1, REGEN2, or REGEN3, these pins can be programmed as part of the power-up sequence to enable external devices such as external SMPSs. The REGEN1 and REGEN3 signals are at the VRTC voltage level and the REGEN2 signal is at the VIO voltage level.

The PRIMARY_SECONDARY_PAD1 and PRIMARY_SECONDARY_PAD2 registers control selection between primary and secondary functions.

When configured as primary functions, all GPIOs are controlled through the following set of registers:

  • GPIO_DAT_DIR: Configures individually each GPIO direction (read and write)
  • GPIO_DATA_IN: Data line-in when configured as an input (read only)
  • GPIO_DATA_OUT: Data line-out when configured as an output (read and write)
  • GPIO_DEBOUNCE_EN: Enables individually each GPIO debouncing (read and write)
  • GPIO_CTRL: Global GPIO control to enable and disable all GPIOs (read and write)
  • GPIO_CLEAR_DATA_OUT: Clears individually each GPIO data out (write only)
  • GPIO_SET_DATA_OUT: Sets individually each GPIO data out (write only)
  • PU_PD_GPIO_CTRL1, PU_PD_GPIO_CTRL2: Configures each line pullup and pulldown (read and write)
  • OD_OUTPUT_GPIO_CTRL: Enables individual output open drain (read and write)

When configured as secondary functions, none of the GPIO control registers (see Table 5-11) affect GPIO lines. The line configurations (pullup, pulldown, or open drain) for secondary functions are held in a separate register set as well as specific function settings.