JAJSLW7B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
Figure 8-41 shows the timing diagram of the TPS6593-Q1 after the first supply detection.
tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table.
BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us time-interval needed for the cyclic redundancy check on the register map and the SRAM.
The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to Section 8.4.1.5 for more details.
The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the power up sequence is completed.