Table 5-1 Summary of the Power Providers

5.1.1.1 VDD1 DC-DC Regulator

5.1.1.1.1 VDD1 DC-DC Regulator Characteristics

The VDD1 DC-DC regulator is a stepdown DC-DC converter with a configurable output voltage. The programming of the output voltage and the characteristics of the DC-DC converter are SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or in power-down mode when it is not in use. Table 5-3 describes the regulator characteristics.

Table 5-2 Part Names With Corresponding VDD1 Current Support

DEVICE NAME	VDD1 CURRENT SUPPORT
TPS65920A2ZCH (some bug fixes, see errata)	1.2 A
TPS65920A2ZCHR (some bug fixes, see errata)	1.2 A
TPS65930A2ZCH (some bug fixes, see errata)	1.2 A
TPS65930A2ZCHR (some bug fixes, see errata)	1.2 A

Table 5-3 VDD1 DC-DC Regulator Characteristics

PARAMETER	COMMENTS	MIN	TYP	MAX	UNIT
Input voltage range		2.7	3.6	4.5	V
Output voltage		0.6		1.45	V
Output voltage step	Covering the 0.6-V to 1.45-V range		12.5		mV
Output accuracy(1)	0.6 V to < 0.8 V	–6%		6%
	0.8 V to 1.45 V	–4%		4%
Switching frequency			3.2		MHz
Conversion efficiency(2), Figure 5-2 in active mode	IO = 10 mA, sleep		82%
	100 mA < IO < 400 mA		85%
	400 mA < IO < 600 mA		80%
	600 mA < IO < 800 mA		75%
Output current	Active mode			1.2	A
	Sleep mode			10	mA
Ground current (IQ)	Off at 30°C			3	μA
	Sleep, unloaded		30	50
	Active, unloaded, not switching			300
Short-circuit current	VIN = VMax		2.2		A
Load regulation	0 < IO < IMax			20	mV
Transient load regulation(3)	IO = 10 mA to (IMax/2) + 10 mA, Maximum slew rate is IMax/2/100 ns	–65		50	mV
Line regulation				10	mV
Transient line regulation	300 mVPP ac input, 10-μs rise and fall time			10	mV
Start-up time			0.25	1	ms
Recovery time	From sleep mode to on mode with constant load		<10	100	μs
Slew rate (rising or falling)(4)		4	8	16	mV/μs
Output shunt resistor (pulldown)			500	700	Ω
External coil	Value	0.7	1	1.3	μH
	Data capture record (DCR)			0.1	Ω
	Saturation current	1.8			A
External capacitor(5)	Value	8	10	12	μF
	Equivalent series resistance (ESR) at switching frequency	0		20	mΩ

(1) Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process)

(2) VBAT = 3.8 V, VDD1 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, L_DCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ

(3) Output voltage must discharge the load current completely and settle to its final value within 100 μs.

(4) Load current varies proportionally with the output voltage. The slew rate is for increasing and decreasing voltages, and the maximum load current is 1.1 A.

(5) Under current load condition step:
Imax/2 (550 mA) in 100 ns with a ±20% external capacitor accuracy or
Imax/3 (367 mA) in 100 ns with a ±50% external capacitor accuracy

See Table 3-2 for how to connect the VDD1/2 DC-DC converter when it is not in use.

Figure 5-2 shows the efficiency of the VDD1 DC-DC regulator in active mode and sleep mode.

Figure 5-2 VDD1 DC-DC Regulator Efficiency

5.1.1.1.2 External Components and Application Schematics

Figure 5-3 is an application schematic with the external components on the VDD1 DC-DC regulator.

Figure 5-3 VDD1 DC-DC Application Schematic

NOTE

For the component values, see Table 5-48.

5.1.1.2 VDD2 DC-DC Regulator

5.1.1.2.1 VDD2 DC-DC Regulator Characteristics

The VDD2 DC-DC regulator is a programmable output stepdown DC-DC converter with an internal field effect transistor (FET). Like the VDD1 regulator, the VDD2 regulator can be placed in sleep or power-down mode and is SmartReflex-compatible. The VDD2 regulator differs from VDD1 in its current load capability. Table 5-4 describes the regulator characteristics.

Table 5-4 VDD2 DC-DC Regulator Characteristics

PARAMETER	COMMENTS	MIN	TYP	MAX	UNIT
Input voltage range		2.7	3.6	4.5	V
Output voltage		0.6	1	1.5	V
Output voltage step	Covering the 0.6-V to 1.45-V range, 1.5 V is a single programmable value		12.5		mV
Output accuracy(1)	0.6 V to < 0.8 V	–6%		6%
	0.8 V to 1.5 V	–4%		4%
Switching frequency			3.2		MHz
Conversion efficiency(2), Figure 5-4 in active mode	IO = 10 mA, sleep		82%
	100 mA < IO < 300 mA		85%
	300 mA < IO < 500 mA		80%
Output current	Active mode			600	mA
	Sleep mode			10	mA
Ground current (IQ)	Off at 30°C			1	μA
	Sleep, unloaded			50
	Active, unloaded, not switching			300
Short-circuit current	VIN = VMax		1.2		A
Load regulation	0 < IO < IMax			20	mV
Transient load regulation(3)	IO = 10 mA to (IMax/2) + 10 mA, Maximum slew rate is IMax/2/100 ns	–65		50	mV
Line regulation				10	mV
Transient line regulation	300 mVPP ac input, 10-μs rise and fall time			10	mV
Output shunt resistor (internal pulldown)			500	700	Ω
Start-up time			0.25	1	ms
Recovery time	From sleep mode to on mode with constant load		25	100	μs
Slew rate (rising or falling)(4)		4	8	16	mV/μs
External coil	Value	0.7	1	1.3	μH
	DCR			0.1	Ω
	Saturation current	900			mA
External capacitor(5)	Value	8	10	12	μF
	ESR at switching frequency	0		20	mΩ

(1) Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process)

(2) VBAT = 3.8 V, VDD2 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, L_DCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ

(3) Output voltage needs to discharge the load current completely and settle to its final value within 100 μs.

(4) Load current varies proportionally with the output voltage. The slew rate is for both increasing and decreasing voltages and the maximum load current is 600 mA.

(5) Under current load condition step:
Imax/2 (300 mA) in 100 ns with a ±20% external capacitor accuracy or
Imax/3 (200 mA) in 100 ns with a ±50% external capacitor accuracy

See Table 3-2 for how to connect the VDD1/2 DC-DC converter when it is not in use.

Figure 5-4 shows the efficiency of the VDD2 DC-DC regulator in active mode and sleep mode.

Figure 5-4 VDD2 DC-DC Regulator Efficiency

5.1.1.2.2 External Components and Application Schematics

Figure 5-5 is an application schematic with the external components on the VDD2 DC-DC regulator.

Figure 5-5 VDD2 DC-DC Application Schematic

NOTE

For the component values, see Table 5-48.

5.1.1.3 VIO DC-DC Regulator

5.1.1.3.1 VIO DC-DC Regulator Characteristics

The I/O and memory DC-DC regulator is a 600-mA stepdown DC-DC converter (internal FET) with two output voltage settings. It supplies the memories and all I/O ports in the application and is one of the first power providers to switch on in the power-up sequence. This DC-DC regulator can be placed in sleep or power-down mode; however, care must be taken in the sequencing of this power provider, because numerous ESD blocks are connected to this supply. Table 5-5 describes the regulator characteristics.

Table 5-5 VIO DC-DC Regulator Characteristics

PARAMETER	COMMENTS	MIN	TYP	MAX	UNIT
Input voltage range		2.7	3.6	4.5	V
Output voltage(1)			1.8 1.85		V
Output accuracy (2)		–4%		4%
		–3%		3%
Switching frequency			3.2		MHz
Conversion efficiency(3)Figure 5-6 in active mode	IO = 10 mA, sleep		85%
	100 mA < IO < 400 mA		85%
	400 mA < IO < 600 mA		80%
Output current	On mode			700	mA
	Sleep mode			10
Ground current (IQ)	Off at 30°C			1	μA
	Sleep, unloaded			50
	Active, unloaded, not switching			300
Load transient(4)				50	mV
Line transient	300 mVPP ac, input rise and fall time 10 μs			10	mV
Start-up time			0.25	1	ms
Recovery time	From sleep mode to on mode with constant load		<10	100	μs
Output shunt resistor (internal pulldown)			500	700	Ω
External coil	Value	0.7	1	1.3	μH
	DCR			0.1	Ω
	Saturation current	900			mA
External capacitor	Value	8	10	12	μF
	ESR at switching frequency	1		20	mΩ

(1) This voltage is tuned according to the platform and transient requirements.

(2) ±4% accuracy includes all the variation (line and load regulation, line and load transient, temperature, process)
±3% accuracy is dc accuracy only.

(3) VBAT = 3.8 V, VIO = 1.8 V, Fs = 3.2 MHz, L = 1 μH, L_DCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ

(4) Load transient can also be specified as 0 < I_O < I_OUTmax/2, Δt = 1 μs, 100 mV but this is not included in ±4% accuracy.

Figure 5-6 shows the efficiency of the VIO DC-DC regulator in active mode and sleep mode.

Figure 5-6 VIO DC-DC Regulator Efficiency
Output Voltage = 1.2 V, V_BAT = 3.8 V

5.1.1.3.2 External Components and Application Schematics

Figure 5-7 is an application schematic with the external components on the VIO DC-DC regulator.

Figure 5-7 VIO DC-DC Application Schematic

NOTE

For the component values, see Table 5-48.

5.1.1.4 VDAC LDO Regulator

The VDAC programmable LDO regulator is a high-PSRR, low-noise linear regulator that powers the host processor dual-video DAC. It is controllable with registers through I²C and can be powered down. Table 5-6 describes the regulator characteristics.

5.1.1.5 VPLL1 LDO Regulator

The VPLL1 programmable LDO regulator is a high-PSRR, low-noise, linear regulator used for the host processor PLL supply. Table 5-7 describes the regulator characteristics.

5.1.1.6 VMMC1 LDO Regulator

The VMMC1 LDO regulator is a programmable linear voltage converter that powers the multimedia card (MMC) slot. It includes a discharge resistor and overcurrent protection (short-circuit). This LDO regulator can also be turned off automatically when MMC card extraction is detected. The VMMC1 LDO can be powered through an independent supply other than the battery; for example, a charge pump. In this case, the input from the VMMC1 LDO can be higher than the battery voltage. Table 5-8 describes the regulator characteristics.

5.1.1.7 VAUX2 LDO Regulator

The VAUX2 general-purpose LDO regulator powers the auxiliary devices. Table 5-9 describes the regulator characteristics.

5.1.1.8 Output Load Conditions

Table 5-10 lists the regulators that power the device, and the output loads associated with them.

5.1.1.9 Charge Pump

The charge pump generates a 4.8-V (nominal) power supply voltage from the battery to the VBUS pin. The input voltage range is 2.7 to 4.5 V for the battery voltage. The charge pump operating frequency is 1 MHz.

The charge pump tolerates 7 V on VBUS when it is in power-down mode. The charge pump integrates a short-circuit current limitation at 450 mA. Table 5-11 lists the charge pump output load conditions.

5.1.1.10 USB LDO Short-Circuit Protection Scheme

The short-circuit current for the LDOs and DC-DCs in the TPS65920 and TPS65930 devices is approximately twice the maximum load current. When the output of the block is shorted to ground, the power dissipation can exceed the 1.2-W requirement if no action is taken. A short-circuit protection scheme is included in the TPS65920 and TPS65930 devices to ensure that if the output of an LDO or DC-DC is short-circuited, the power dissipation does not exceed the 1.2-W level.

The three USB LDOs, VRUSB3V1, VRUSB1V8, and VRUSB1V5, are included in this short-circuit protection scheme, which monitors the LDO output voltage at a frequency of 1 Hz and generates an interrupt (sc_it) when a short-circuit is detected.

The scheme compares the LDO output voltage to a reference voltage and detects a short-circuit if the LDO voltage drops below this reference value (0.5 or 0.75 V programmable). In the case of the VRUSB3V1 and VRUSB1V8 LDOs, the reference is compared with a divided down voltage (1.5 V typical).

If a short-circuit is detected on VRUSB3V1, the power subchip FSM switches this LDO to sleep mode.

If a short-circuit is detected on VRUSB1V8 or VRUSB1V5, the power subchip FSM switches off the relevant LDO.

Table 5-12 Voltage Reference Characteristics

5.1.3.1 Backup Battery Charger

If the backup battery is rechargeable, it can be recharged from the main battery. A programmable voltage regulator powered by the main battery allows recharging of the backup battery. The backup battery charge must be enabled using a control bit register. Recharging starts when two conditions are met:

• Main battery voltage > backup battery voltage
• Main battery > 3.2 V

The comparators of the backup battery system (BBS) give the two thresholds of the backup battery charge startup. The programmed voltage for the charger gives the end-of-charge threshold. The programmed current for the charger gives the charge current.

Overcharging is prevented by measurement of the backup battery voltage through the GP ADC. Table 5-13 lists the characteristics of the backup battery charger.

5.1.3.2 Battery Monitoring and Threshold Detection

5.1.3.3 VRRTC LDO Regulator

The VRRTC voltage regulator is a programmable, low dropout, linear voltage regulator supplying (1.5 V) the embedded real-time clock (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart. The VRRTC regulator is also the supply voltage of the power-management digital state-machine. The VRRTC regulator is supplied from the UPR line, switched on by the main or backup battery, depending on the system state. The VRRTC output is present as long as a valid energy source is present. The VRRTC line is supplied by an LDO when VBAT > 2.7, and a clamp circuit when in backup mode. Table 5-15 describes the regulator characteristics.

Table 5-16 Power Consumption

Table 5-17 Regulator State Depending on Use Case

5.1.5.1 Boot Modes

Table 5-18 lists the modes corresponding to BOOT0–BOOT1.

5.1.5.2 Process Modes

This parameter defines:

• The boot voltage for the host core
• The boot sequence associated with the process
• The dynamic voltage and frequency scaling (DVFS) protocol associated with the process

5.1.5.3 Power-On Sequence

5.1.5.3.1 Timing Before Sequence_Start

Sequence_Start is a symbolic internal signal to ease the description of the power sequences. It occurs according to the events shown in Figure 5-8.

Figure 5-8 Timing Before Sequence Start

5.1.5.3.2 Power-On Sequence

Figure 5-9 describes the timing and control that must occur in the OMAP3 mode. Sequence_Start is a symbolic internal signal to ease the description of the power sequences. It occurs according to the events shown in Figure 5-8.

Figure 5-9 Timings–Power On in OMAP3 Mode

5.1.5.3.3 Power On in Slave_C021 Mode

Figure 5-10 describes the timing and control that must occur in the Slave_C021 mode. Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs according to the different events detailed in Figure 5-8.

Figure 5-10 Timings—Power On in Slave_C021 Mode

5.1.5.4 Power-Off Sequence

This section describes the signal behavior required to power down the system.

5.1.5.4.1 Power-Off Sequence

Figure 5-11 shows the timing and control that occur during the power-off sequence in master modes.

NOTE:

All of these timings are typical values with the default setup (depending on the resynchronization between power domains, state machinery priority, etc.).

Figure 5-11 Power-Off Sequence in Master Modes

Because of the internal frequency used by Power STM switching from 3 to 1.5 MHz when the HF clock value is 19.2 MHz, if the HF clock value is not 19.2 MHz (with HFCLK_FREQ bit field values set accordingly in the CFG_BOOT register), the delay between DEVOFF and NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by two (approximately 9 μs).

The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master mode.

5.2.1.1 Backup Battery

The TPS65030 and TPS65920 devicesdevice implement a backup mode in which a backup battery can keep the RTC running to maintain clock and time information even if the main supply is not present. If the backup battery is rechargeable, the device also provides a backup battery charger so it can be recharged when the main battery supply is present.

The backup domain powers the following:

• Internal 32.768-kHz crystal oscillator
• RTC
• Eight general-purpose (GP) storage registers
• Backup domain low-power regulator (VBRTC)

Table 5-20 System States

Table 5-21 HS-USB Interface Timing Requirements

Table 5-22 HS-USB Interface Switching Requirements⁽¹⁾

Table 5-23 USB-CEA Carkit Interface Timing Parameters

Table 5-24 USB-CEA Carkit UART Timings

5.3.4.1 HS Differential Receiver

The HS receiver consists of the following blocks:

• A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a nonreturn to zero inverted (NRZI) decoder, bit unstuffing, and serial-to-parallel converter to generate the UTMI DATAOUT

Table 5-25 lists the characteristics of the HS differential receiver.

5.3.4.2 HS Differential Transmitter

The HS transmitter is always operated on the UTMI parallel interface. The parallel data on the interface is serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM, depending on the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for signaling.

A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes the impedance seen by the transmitter to double, thereby doubling the differential amplitude seen on the DP/DM lines.

Table 5-26 lists the characteristics of the HS differential transmitter.

5.3.4.3 CEA/UART Driver

Table 5-27 lists the characteristics of the CEA/UART driver.

5.3.4.4 Pullup/Pulldown Resistors

Table 5-28 lists the characteristics of pullup/pulldown resistors.

5.3.5.1 OTG VBUS Electrical Characteristics

Table 5-29 lists the electrical characteristics of the OTG VBUS.

5.3.5.2 OTG ID Electrical Characteristics

Table 5-30 lists the electrical characteristics of OTG ID.

Table 5-31 MADC Electrical Characteristics

Table 5-32 Analog Input Voltage Range

5.4.3.1 Sequence Conversion Time (Real-Time or Nonaborted Asynchronous)

Table 5-33 lists the sequence conversion timing characteristics.

Table 5-33 is illustrated in Figure 5-17, which is a conversion sequence general timing diagram. The Busy parameter indicates that a conversion sequence is running, and the channel N result register parameter corresponds to the result register of the RT/GP selected channel.

Figure 5-17 Conversion Sequence General Timing Diagram

Table 5-34 LED Driver Electrical Characteristics

5.7.2.1 Clock Source Requirements

Table 5-35 lists the input clock requirements.

5.7.2.2 HFCLKIN

HFCLKIN can be a square- or a sine-wave input clock. If a square-wave input clock is provided, it is recommended to switch the block to bypass mode to avoid loading the clock.

Figure 5-21 shows the HFCLKIN clock distribution.

Figure 5-21 HFCLKIN Clock Distribution

When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the CLKREQ pin. As a result, the TPS65920/TPS65930 device immediately sets CLKEN to 1 to warn the clock provider in the system about the clock request and starts a timer (maximum of 5.2 ms using the 32.768-kHz clock). When the timer expires, the TPS65920/TPS65930 device opens a gated clock, the timer automatically reloads the defined value, and a high-frequency output clock signal is available through the HFCLKOUT pin. The output drive of HFCLKOUT is programmable (minimum load 10 pF, maximum load 40 pF) and must be at 40 pF by default.

With a register setting, the mirroring of CLKEN can be enabled on CLKEN2. When this mirroring feature is not enabled, CLKEN2 can be used as a general-purpose output controlled through I²C accesses.

CLKREQ, when enabled, has a weak pulldown resistor to support the wired-OR clock request.

Figure 5-22 shows an example of the wired-OR clock request.

Figure 5-22 Example of Wired-OR Clock Request

The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround support, the NSLEEP1 and NSLEEP2 signals can also be used as a clock request even if it is not their primary goal. By default, this feature is disabled and must be enabled individually by setting the register bits associated with each signal.

When the external clock signal is present on the HFCLKIN ball, it is possible to use this clock instead of the internal RC oscillator and then synchronize the system on the same clock. The RC oscillator can then go to idle mode.

Table 5-36 lists the input clock electrical characteristics of the HFCLKIN input clock.

Table 5-37 lists the input clock timing requirements of the HFCLKIN input clock when the source is a square wave. Figure 5-23 shows the HFCLKIN squared input clock timings.

Figure 5-23 HFCLKIN Squared Input Clock

5.7.2.3 32-kHz Input Clock

A 32.768-kHz input clock (often abbreviated to 32-kHz) generates the clocks for the RTC. It has a low-jitter mode where the current consumption increases for lower jitter. It is possible to use the 32-kHz input clock with an external crystal or clock source. Depending on the mode chosen, the 32K oscillator is configured one of two ways:

• An external 32.768-kHz crystal through the 32KXIN/32KXOUT balls (see Figure 5-24). This configuration is available only for master mode (for more information, see Section 4.7).
• An external square/sine wave of 32.768 kHz through 32KXIN with amplitude equal to 1.8 or 1.85 V (see Figure 5-26, Figure 5-27, and Figure 5-28). This configuration is available for the master and slave modes (for more information, see Section 4.7).

5.7.2.3.1 External Crystal Description

Figure 5-24 shows the 32-kHz oscillator block diagram with crystal in master mode.

NOTE:

Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.

Figure 5-24 32-kHz Oscillator Block Diagram In Master Mode With Crystal

CXIN and CXOUT represent the total capacitance of the printed circuit board (PCB) and components, excluding the crystal. Their values depend on the datasheet of the crystal, the internal capacitors, and the parallel capacitor. The frequency of the oscillations depends on the value of the capacitors. The crystal must be in the fundamental mode of operation and parallel resonant.

NOTE

For the values of CXIN and CXOUT, see Table 5-48.

Table 5-38 lists the required electrical constraints.

Table 5-38 Crystal Electrical Characteristics

PARAMETER	MIN	TYP	MAX	UNIT
Parallel resonance crystal frequency		32.768		kHz
Input voltage, Vin (normal mode)	1.0	1.3	1.55	V
Internal capacitor on each input (Cint)		10		pF
Parallel input capacitance (Cpin)			1	pF
Nominal load cap on each oscillator input CXIN and CXOUT(1)	CXIN = CXOUT = Cosc*2 – (Cint + Cpin)			pF
Pin-to-pin capacitance		1.6	1.8	pF
Crystal ESR(2)			75	kΩ
Crystal shunt capacitance, CO			1	pF
Crystal tolerance at room temperature, 25°C	–30		30	ppm
Crystal tolerance versus temperature range (–40°C to 85°C)	–200		200	ppm
Maximum drive power			1	μW
Operating drive level			0.5	μW

(1) Nominal load capacitor on each oscillator input defined as CXIN = CXOUT = Cosc*2 – (Cint + Cpin). Cosc is the load capacitor defined in the crystal oscillator specification, Cint is the internal capacitor, and Cpin is the parallel input capacitor.

(2) The crystal motional resistance Rm relates to the equivalent series resistance (ESR) by the following formula:

Measured with the load capacitance specified by the crystal manufacturer. If CXIN = CXOUT = 10 pF, C_L = 5 pF. Parasitic capacitance from the package and board must also be considered.

When selecting a crystal, the system design must consider the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system.

Table 5-39 and Table 5-40 list the switching characteristics of the oscillator and the timing requirements of the 32.768-kHz input clock. Figure 5-25 shows the crystal oscillator output in normal mode.

Table 5-39 Base Oscillator Switching Characteristics

NAME	PARAMETER DESCRIPTION		MIN	TYP	MAX	UNIT
fP	Oscillation frequency			32.768		kHz
tSX	Start-up time				0.5	s
IDDA	Active current consumption	LOJIT <1:0> = 00			1.8	μA
		LOJIT <1:0> = 11			8
IDDQ	Current consumption	Low battery mode (1.2 V)			1	μA
		Startup			8

Table 5-40 32-kHz Crystal Input Clock Timing Requirements

NAME	PARAMETER DESCRIPTION		MIN	TYP	MAX	UNIT
OC0	1/tC(32KHZ)	Frequency, 32 kHz		32.768		kHz
OC1	tW(32KHZ)	Pulse duration, 32 kHz low or high	0.40*tC(32KHZ)		0.60*tC(32KHZ)	μs

Figure 5-25 32-kHz Crystal Input

5.7.2.3.2 External Clock Description

When an external 32K clock is used instead of a crystal, three configuration can be used:

• A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The 32KXOUT pin can be driven to a dc value of the square- or sine-wave amplitude divided by 2. This configuration, shown in Figure 5-26, is recommended if a large load is applied on the 32KXOUT pin.
• A square- or sine-wave input can be applied to the 32KXIN pin with amplitude of 1.85 or 1.8 V. The 32KXOUT pin can be left floating. This configuration, showed in Figure 5-27, is used if no charge is applied on the 32KXOUT pin.
• The oscillator is in bypass mode and a square-wave input can be applied to the 32KXIN pin with amplitude of 1.8 V. The 32KXOUT pin can be left floating. This configuration, shown in Figure 5-28, is used if the oscillator is in bypass mode.

1. Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.

Figure 5-26 32-kHz Oscillator Block Diagram Without Crystal Option 1

1. Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.

Figure 5-27 32-kHz Oscillator Block Diagram Without Crystal Option 2

1. Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V.

Figure 5-28 32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3

Table 5-41 lists the electrical constraints required by the 32-kHz input square- or sine-wave clock.

Table 5-41 32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics

NAME	PARAMETER DESCRIPTION	MIN	TYP	MAX	UNIT
f	Frequency	32.768			kHz
CI	Input capacitance		35		pF
CFI	On-chip foot capacitance to GND on each input (see Figure 5-26, Figure 5-27, and Figure 5-28)		10		pF
VPP	Square-/sine-wave amplitude in bypass mode or not		1.8(1)		V
VIH	Voltage input high, square wave in bypass mode	0.8			V
VIL	Voltage input low, square wave in bypass mode			0.6	V

(1) Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface.

Table 5-42 lists the timing requirements of the 32-kHz square-wave input clock.

Table 5-42 32-kHz Square-Wave Input Clock Source Timing Requirements

NAME	PARAMETER	DESCRIPTION	MIN	TYP	MAX	UNIT
CK0	1/tC(32KHZ)	Frequency, 32 kHz	32.768			MHz
CK1	tW(32KHZ)	Pulse duration, 32 kHz low or high	0.45*tC(32KHZ)		0.55*tC(32KHZ)	μs
CK3	tR(32KHZ)	Rise time, 32 kHz(1)			0.1*tC(32KHZ)	μs
CK4	tF(32KHZ)	Fall time, 32 kHz(1)			0.1*tC(32KHZ)	μs

(1) The capacitive load is 30 pF.

Figure 5-29 shows the 32-kHz square- or sine-wave input clock.

Figure 5-29 32-kHz Square- or Sine-Wave Input Clock

5.7.3.1 32KCLKOUT Output Clock

Figure 5-30 is the block diagram for the 32.768-kHz clock output.

Figure 5-30 32.768-kHz Clock Output Block Diagram

The TPS65920/TPS65930 device has an internal 32.768-kHz oscillator connected to an external 32.768-kHz crystal through the 32KXIN/32KXOUT balls or an external digital 32.768-kHz clock through the 32KXIN input (see Figure 5-30). The TPS65920/TPS65930 device also generates a 32.768-kHz digital clock through the 32KCLKOUT pin and can broadcast it externally to the application processor or any other devices. The 32KCLKOUT clock is broadcast by default in TPS65920/TPS65930 active mode, but can be disabled if it is not used.

The 32.768-kHz clock (or signal) is also used to clock the RTC embedded in the TPS65920/TPS65930 device. The RTC is not enabled by default. The host processor must set the correct date and time and enable the RTC functionality.

The 32KCLKOUT output buffer can drive several devices (up to 40-pF load). At startup, 32KCLKOUT must be stabilized (frequency/duty cycle) before the signal output. Depending on the startup conditions, this can delay the startup sequence.

Table 5-43 lists the electrical characteristics of the 32KCLKOUT output clock.

Table 5-44 lists the output clock switching characteristics. Figure 5-31 shows the 32KCLKOUT output clock waveform.

Figure 5-31 32KCLKOUT Output Clock

5.7.3.2 HFCLKOUT Output Clock

Table 5-45 lists the electrical characteristics of the HFCLKOUT output clock.

Table 5-46 lists the switching characteristics of the HFCLKOUT output clock.

Figure 5-32 shows the HFCLKOUT output clock waveform.

Figure 5-32 HFCLKOUT Output Clock

5.7.3.3 Output Clock Stabilization Time

Figure 5-33 shows the 32KCLKOUT and HFCLKOUT clock stabilization time.

NOTE:

Tstartup, Delay1, and Delay2 depend on the boot mode (see Section 5.1.5).

NOTE:

Ensure that the high frequency oscillator start-up time is in spec for the boot mode used. During power-up the internal delay, Delay1 above is fixed (5.2 ms and 5.3 ms depending on boot mode). The start-up time for the oscillator must be less than the fixed delay.

Figure 5-33 32KCLKOUT and HFCLKOUT Clock Stabilization Time

Figure 5-34 shows the HFCLKOUT behavior.

Figure 5-34 HFCLKOUT Behavior