The Fixed Device Power portion of the
FSM engine manages the power up of the device before the power rails are fully
enabled and ready to power external loadings, and the power down of the device when
in the event of insufficient power supply or device or system error conditions.
While the device is in one of the Hardware Device Powers states, the
ENABLE_DRV bit remains low.
The definitions and transition
triggers of the Device Power States are fixed and cannot be reconfigured.
Following are the definitions of the
Device Power states:
NO SUPPLYThe device is not powered by a valid energy source on the system power
rail. The device is completely powered off.
BACKUP (RTC backup battery)The device is not powered by a valid supply on the system power rail
(VCCA < VCCA_UVLO); a backup power source, however, is present and is
within the operating range of the LDOVRTC. The RTC clock counter remains
active in this state if it has been previously activated by appropriate
register enable bit. The calendar function of the RTC block is
activated, but not accessible in this state. Customer has the option to
enable the shelf mode by
disconnecting the VCCA supply completely, even while the backup battery
is connected to the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state
and enters the NO SUPPLY state under VCCA_UVLO condition to reduce
current draining from the backup battery.
LP_STANDBYThe device can enter this state from a mission state after receiving a
valid OFF request
or an I2C trigger,
and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC clock counter and the RTC Alarm or
Timer Wake-up functions are active if they have been previously
activated by appropriate register enable bit. Low Power
Wake-up input monitor in the LDOVRTC domain (LP_WKUP secondary
function through GPIO3 or GPIO4) and the on request monitors are also enabled in this state. When
a logic level transition from high-to-low or low-to-high with a
minimum pulse length of tLP_WKUP is detected on the
assigned LP_WKUP pin, or if the device detects a valid
on-request or a wake-up signal
from the RTC block, the device proceeds to power
up the device and reach the default mission state. More details
regarding the LP_WAKE function can be found in Section 8.4.1.2.4.5.
INITThe device is powered by a valid supply on the system power rail (VCCA ≥
VCCA_UV). If the device was previously in LP_STANDBY state, it has
received an external wake-up signal at the LP_WKUP1/2
pins, the RTC alarm or timer wake-up
signal, or an On Request from the nPWRON/ENABLE
pin. Device digital and monitor circuits are powered up. The PMIC reads
its internal NVM memory in this state and configures default values to
registers, IO configuration and FSM accordingly.
BOOT BISTThe device is running the built-in self-test routine
which includes both the LBIST and the ABIST/CRC. An option is available
to shorten the device power up time from the NO_SUPPLY state by setting
the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also
set the FAST_BIST = '1' to skip LBIST after the device wakes up from the
LP STANDBY state. When the device arrives at this state from the
SAFE_RECOVERY state, LBIST is automatically skipped if it has not
previously failed. If LBIST failed, but passed after multiple re-tries
before exceeding the recovery counter limit, the device powers up
normally. The following NVM bits are additional options which can be set
to disable parts of the ABIST/CRC tests if further sequence time
reduction is required:
REG_CRC_EN = '0':
disables the register map and SRAM CRC check
VMON_ABIST_EN =
'0': disables the ABIST for the VMON OV/UV function
Note: Note: the BIST
tests are executed as parallel processes, and the longest process
determines the total BIST duration
RUNTIME BISTA request was received from the MCU to exercise a
run-time built-in self-test (RUNTIME_BIST) on the device. No rails are
modified and all external signals, including all I2C or SPI
interface communications, are ignored during BIST. If the device passed
BIST, it resumes the previous operation. If the device failed BIST, it
shuts down all of the regulator outputs and proceed to the SAFE RECOVERY
state. In order to avoid a register CRC error, all register writes must
be avoided after the request for the BIST operation until the device
pulls the nINT pin low to indicate the completion of BIST. The results
of the BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT
bits.
Note:
For executing the
RUNTIME_BIST, the system software must perform following
steps:
Before
RUNTIME_BIST request:
1) clear all
LDOx_VMON_EN bits to 0
2) Set
VCCA_UV_MASK, VCCA_OV_MASK, all BUCKx_UV_MASK, all
BUCKx_OV_MASK, all LDOx_UV_MASK and all LDOx_OV_MASK bits to
1
After completion
of RUNTIME_BIST:
1) Clear
VCCA_UV_MASK, VCCA_OV_MASK, all BUCKx_UV_MASK and all
BUCKx_OV_MASK bits to 0
2) Set all
LDOx_VMON_EN bits to 1
3) After 1
millisecond (if LDOx_SLOW_RAMP=0) respectively 3.5 milliseconds
(if LDOx_SLOW_RAMP=1), clear all LDOx_UV_MASK and LDOx_OV_MASK
bits to 0
SAFE RECOVERYThe device meets the qualified error condition for immediate or ordered
shutdown request. If the error is recovered within the recovery time interval or
meets the restart condition, the device increments the recovery
counter, and returns to INIT state if the recovery counter value
does not exceed the threshold value. If the recovery counter exceeds
the threshold value or if the error cannot be recovered, such as the die
temperature cannot be reduced to < TWARN, or if VCCA stays above OVP threshold, the device stays in SAFE RECOVERY state
until a supply power cycle occurs.
When multiple system conditions occur
simultaneously which demands power state arbitration, the device goes to the higher
priority state according to the following priority order:
NO SUPPLY
BACKUP
SAFE_RECOVERY
LP_STANDBY
MISSION STATES
Figure 8-39 shows the power transition states of the FSM engine.