TPS65980 Thunderbolt™ Bus Power Buck/Boost
- SLVSCK1A April 2014 – April 2014 TPS65980
  
  PRODUCTION DATA.

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DATA SHEET

TPS65980 Thunderbolt™ Bus Power Buck/Boost

1 Features

Powered From Thunderbolt™ Bus
2.5-V to 15.75-V Input
3.3-V Outputs
Cable Power Out Current Limit
Thermal Shutdown

2 Applications

Thunderbolt™/Thunderbolt™ 2 Systems
Bus Powered Systems
Power Management Systems

3 Description

The TPS65980 DC/DC switching regulator that receives power from a Thunderbolt™ or Thunderbolt™ 2 power bus ranging from 2.5-V to 15.75-V and generates three separate 3.3-V supply outputs.

The TBT_OUT supply provides power to the local peripheral Thunderbolt™ controller and support circuitry. The CBL_OUT supply provides power back to the Thunderbolt™ cable and has adjustable current limit. The DEV_OUT supply provides power to all other circuitry in the device to perform its designed function.

The TPS65980 is available in a 24-pin
5mm x 4mm x 0.9mm VQFN package.

Device Information⁽¹⁾

DEVICE NAME	PACKAGE	BODY SIZE
TPS65980	VQFN (24)	5mm x 4mm

For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

5 Revision History

Changes from * Revision (April 2014) to A Revision

Revised document to full version. Go

6 Pin Configuration and Functions

VQFN (RHF) 24-Pin

TOP VIEW

VQFN (RHF) 24-Pin

BOTTOM

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	SS	ANALOG	Soft Start Capacitance. This pin sets the soft start ramp rate when the TBT_IN voltage ramps from 0V to high voltage.
2, 3, 4	GND	GND	Device Ground
5	HV_OK	OUTPUT	High Voltage Present Indicator. This pin indicates that a high voltage is present on TBT_IN. The output asserts high when the TBT_IN pin is above the V_HVT voltage and the RESET output is asserting high.
6	RESET	OUTPUT	Reset output indicator. This pin asserts low when TBT_OUT is in under-voltage.
7	CBL_OUT	PWROUT	Current Limited Power Output to Thunderbolt™ Cable. This pin supplies power to the Thunderbolt™ cable. The current limit of this pin is set by the CBL_ILIMIT pin.
8	CBL_ILIMIT	INPUT	Current Limit Set. Logic input that sets the current limit state on the CBL_OUT pin. Tie pin to TBT_OUT for a logic high input.
9	DEV_EN	INPUT	Device Enable Input. When input pin is high, DEV_OUT is high impedance. When input pin low, DEV_OUT is connected to TBT_OUT.
10	GND	ANALOG	Device Ground
11, 12	TBT_OUT	PWROUT	Power Output to Thunderbolt™ circuitry. This pin supplies power to the Thunderbolt™ controller.
13, 14	DEV_OUT	PWROUT	Power Output to peripheral device. This pin supplies power to circuitry not associated with the Thunderbolt™ controller or the Thunderbolt™ cable. It is intended to supply power to the peripheral device main function.
15	CPP	ANALOG	Charge Pump Capacitance Positive Output
16	CPN	ANALOG	Charge Pump Capacitance Negative Output
17, 18	PGND	GND	Buck Controller Power Ground
19, 20	SW	ANALOG	Buck Controller Switch Output
21	BOOT	ANALOG	Buck Controller Bootstrap
22, 23	TBT_IN	PWRIN	Power Input from Thunderbolt™ Cable. This pin is the power supply to the device.
24	COMP	ANALOG	Buck Converter Compensation. This pin provides compensation to the buck converter feedback loop.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
	Input voltage range⁽²⁾	TBT_IN	–0.3	18	V
		DEV_EN	–0.3	3.6
		BOOT	–0.3	25
		BOOT (10 ns transient)	–0.3	27
		BOOT (vs SW)	–0.3	7
		SW	–0.6	18
		SW (10 ns transient)	–2	20
		COMP	–0.3	3.6
		SS	–0.3	3.6
		CBL_ILIMIT	–0.3	3.6
		CPP	–0.3	7.2
		CPN	–0.3	3.6
	Output voltage range⁽²⁾	TBT_OUT, CBL_OUT, DEV_OUT	–0.3	3.6	V
	Output voltage range⁽²⁾	RESET, HV_OK	–0.3	3.6	V
V_diff	Voltage from GND to Thermal Pad		–0.2	0.2	V
	Voltage from PGND to GND		–0.2	0.2	V
T_A	Operating ambient temperature		–40	85	°C
T_J	Operating junction temperature		–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground pin.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	0	2	kV
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	0	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature (unless otherwise noted)

			MIN	MAX	UNIT
TBT_IN	Supply input voltage range		2.5	15.75	V
V_I	Input voltage range	DEV_EN	–0.1	3.6
		BOOT	–0.1	25
		SW	–0.6	16.5
		COMP	–0.1	3.6
		SS	–0.1	3.6
		CBL_ILIMIT	–0.1	3.6
		CPP	–0.1	7.2
		CPN	–0.1	3.6
V_O	Output voltage range	TBT_OUT, CBL_OUT, DEV_OUT	–0.1	3.6	V
V_O	Output voltage range	RESET, HV_OK	–0.1	3.6	V
T_A	Operating free-air temperature		–40	85	°C
T_J	Operating junction temperature		–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS65980	UNIT
		RHF
		24 PIN
R_θJA	Junction-to-ambient thermal resistance	30.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	26.9
R_θJB	Junction-to-board thermal resistance	8.2
ψ_JT	Junction-to-top characterization parameter	0.3
ψ_JB	Junction-to-board characterization parameter	8.2
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Unless otherwise noted all specifications applies over the V_{TBT_IN} range and operating ambient temperature of
–40°C ≤ T_A ≤ 85°C, C_{TBT_IN} = 22 µF, C_{TBT_OUT} = 10 µF, C_{CBL_OUT} = 1 µF, CSS = 10 nF, and 33 V/µs logic input transitions. Typical values are for V_{TBT_IN} = 12 V and T_A = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES AND CURRENTS
V_{TBT_IN}	TBT_IN Input voltage range		2.5	12	15.75	V
V_{REF_RSTN}	TBT_OUT to RESET clear high	TBT_OUT rising	3	3.1	3.2	V
V_{REF_RSTN}	TBT_OUT to RESET assert low	TBT_OUT falling	2.5	2.6	2.7	V
V_HVTR	TBT_IN to HV_OK assert	TBT_IN rising	4.36	4.5	4.64	V
V_HVTHYST	TBT_IN to HV_OK clear	TBT_IN Falling hysteresis		100		mV
SR_02L	TBT_IN Input slew rate	TBT_IN transition from 0 V to 3.3 V	0.1		30	kV/s
SR_L2H	TBT_IN Input slew rate	TBT_IN transition from 3.3 V to 15 V	0.1		30	kV/s
I_RAMP	Combined output di/dt⁽¹⁾				5	kA/s
Efficiency	Buck converter efficiency	I_LOADTOTAL = 3 A, V_{TBT_IN} = 12 V		87%
Efficiency	Charge pump efficiency	V_{TBT_IN} = 3.3 V, I_LOADTOTAL = 25 mA		47%
POWER OUTPUT PINS (LOW VOLTAGE INPUT)⁽²⁾
V_{TBT_IN}	TBT_IN Input voltage range		2.5	3.3	3.4	V
V_{TBT_OUT}	TBT_OUT Output voltage range⁽³⁾		3.135	3.25	3.4	V
I_{TBT_OUT}	TBT_OUT Load current⁽⁴⁾⁽⁵⁾	RESET high	5		50	mA
I_{TBT_OUT}	TBT_OUT Load current⁽⁴⁾⁽⁵⁾	RESET low			100	µA
POWER OUTPUT PINS (HIGH VOLTAGE INPUT)⁽⁶⁾
V_{TBT_IN}	TBT_IN Input voltage range		10	12	15.75	V
V_{TBT_OUT}	TBT_OUT Output voltage range⁽³⁾	I_LOADTOTAL = 1 A to 3.5 A	3.221	3.27	3.319	V
V_{TBT_OUT}	TBT_OUT Output voltage range⁽³⁾	I_LOADTOTAL = 0.235 A to 3.5 A	3.221	3.27	3.42	V
I_{TBT_OUT}	TBT_OUT Load current⁽⁴⁾		235		1000	mA
V_{CBL_OUT}	CBL_OUT Output voltage range⁽³⁾	ILIMIT = 0, I_{CBL_OUT} = 0 to 720 mA	3.171	3.27	3.319	V
V_{CBL_OUT}	CBL_OUT Output voltage range⁽³⁾	ILIMIT = 1, I_{CBL_OUT} = 0 to 1.44 A	3.12	3.27	3.319	V
V_{DEV_OUT}	DEV_OUT Output Voltage Range	I_{DEV_OUT} = 0 to 2500 mA	3	3.27	3.319	V
POWER OUTPUT PINS (HIGH VOLTAGE INPUT DURING SYSTEM SLEEP)
V_{TBT_IN}	TBT_IN Input voltage range		5.2	12	15.75	V
V_{TBT_OUT}	TBT_OUT DC Output voltage range	I_LOADTOTAL = 1 A to 3.5 A	3.221	3.27	3.319	V
V_{TBT_OUT}	TBT_OUT DC Output voltage range	I_LOADTOTAL = 0.235 A to 3.5 A	3.221	3.27	3.42	V
I_{TBT_OUT}	TBT_OUT Load current		5		31	mA
V_{CBL_OUT}	CBL_OUT Output voltage range⁽³⁾	I_{CBL_OUT} = 0 to 235 mA	3.171	3.27	3.319	V
V_{DEV_OUT}	DEV_OUT Output voltage range	I_{DEV_OUT} = 0 to 700 mA	3	3.3	3.319	V
CABLE OUTPUT (HIGH VOLTAGE INPUT & HIGH VOLTAGE INPUT DURING SLEEP)
V_{CBL_OUT_MON}	CBL_OUT Ramp-up monotonicity⁽⁷⁾	CBL_OUT ramp from off to on			0	mV
V_{CBL_OUT_RIP}	CBL_OUT Voltage ripple	After settling All output combined Load > 1 mA			2	%_P-P
V_{CBL_OUT_RIP}	CBL_OUT Voltage ripple	All output combined Load < 1 mA			40	mV_P=P
I_{LIM_CBLOUT}	CBL_OUT Current limit	ILIMIT = 0	0.8	1.1	1.4	A
I_{LIM_CBLOUT}	CBL_OUT Current limit	ILIMIT = 1	1.6	2.2	2.8	A
t_{LIM_CBLOUT}	Short circuit response time	RCBL_OUT = 0.5 Ω to GND, ILIMIT = 0			500	µs
t_{LIM_CBLOUT}	Short circuit response time	RCBL_OUT = 0.01 Ω to GND, ILIMIT = 0			8	µs
DEV_EN AND ILIMIT INPUT LOGIC
V_IH	High-level input voltage		2.6			V
V_IL	Low-level input voltage				0.6	V
I_IN	Input leakage to GND	V_{DEV_EN} = 3.3V			1	mA
RESET AND HV_OK OUTPUT LOGIC
V_OH	High-level output voltage	I_L = –1.5 mA, Referenced to V_{TBT_OUT}	–250		0	mV
V_OL	Low-level output voltage	I_L = 1.5 mA	0		250	mV
SOFT START⁽³⁾
I_INRUSH	Inrush current di/dt				250	kA/s
THERMAL SHUTDOWN
T_SD	Shutdown temperature		120	135	150	°C
T_SDHYST	Shutdown hysteresis			10		°C

(1) The three voltage outputs (TBT_OUT, CBL_OUT, DEV_OUT) all pull current from a single node. Therefore, the total combined current cannot exceed the maximum di/dt.

(2) CBL_OUT and DEV_OUT are open (high impedance) for this input voltage range.

(3) During light load conditions, the average output voltage may reach 3.5 V with peaks not exceeding 3.42 V.

(4) TBT_OUT load current flows from the TBT_OUT pin when the device is in charge pump mode and pulls the buck converter inductor when the device is in buck mode.

(5) TBT_OUT load current will not go higher than 50mA until after the device asserts HV_OK.

(6) The maximum current supplied by the TPS65980 to all outputs is limited to 3.5 A. Max power depends on the Thunderbolt™ system and how much power is supplied to the input.

(7) A monotonicity of 0 mV means that the output does not have a negative going ramp at anytime during its power up ramp. A ripple of up to 62 mV from the DC/DC will occur.

7.6 Timing Requirements

			MIN	TYP	MAX	UNIT
t_IN2OR	TBT_IN to TBT_OUT On Time	V_{TBT_IN} ≥ 0.9 × V_{TBT_IN(min}) to V_{TBT_OUT} ≥ 0.99 × V_{TBT_OUT(min)} R_{TBT_OUT} = 100 Ω			20	ms
t_IN2OF	TBT_IN to TBT_OUT Off Time	V_{TBT_IN} ≤ 0.9 × V_{TBT_IN(min)} to V_{TBT_OUT} ≤ 0.1 × V_{TBT_OUT(min)} R_{TBT_OUT} = 100 Ω		2.4	4	ms
t_OUT2RR	TBT_OUT to RESETZ High time	V_{TBT_OUT} ≥ V_{REF_RSTN(max)} rising to V_RESET = 0.9 × VOH, C_RESETN = 100 pF			20	µs
t_IN2RF	TBT_IN to RESETZ Low time	V_{TBT_IN} ≤ 0.9 × V_{TBT_IN(min)} to V_RESET = 0.1 × V_OH, C_RESETN = 100 pF			20	ms
t_HV2OKR	TBT_IN Rise to HV_OK	V_{TBT_IN} ≥ V_HVTR to V_{HV_OK} = 0.9 × V_OH C_{HV_OK} = 100 pF			10	µs
t_HV2OKF	TBT_IN Fall to HV_OK	V_{TBT_IN} ≤ V_HVTR-V_HVTHYST to V_{HV_OK} = 0.1 × V_OH, C_{HV_OK} = 100 pF			10	µs
t_HV2CR⁽¹⁾⁽²⁾	HV_OK to CBL_OUT On time	V_{HV_OK}≥ 1.65 V to V_{CBL_OUT} = 2.95 V R_{CB_OUT} = 100 Ω, C_{HV_OK} = 100 pF	0.1		10	ms
t_HV2CF	HV_OK to CBL_OUT Off time	V_{HV_OK} ≤ 1.65 V to V_{CBL_OUT} = 2.95 V R_{CB_OUT} = 100 Ω, C_{HV_OK} = 100 pF			40	µs
t_RCBL	CABLE_OUT Ramp time	V_{CBL_OUT} ramp 10% to 90% C_{CBL_OUT} = 0 to 52 µF	0.1		10	ms
t_DEVEN	DEV_EN to DEV_OUT On time	V_{DEV_EN} ≤ 1.65 V to V_{DEV_OUT} = 2.7 V R_{DEV_OUT} = 100 Ω	0.1		10	ms
t_DEVDIS	DEV_EN to DEV_OUT Off time	V_{DEV_EN} ≥ 1.65V to V_{DEV_OUT} = 2.7 V RDEV_OUT = 100 Ω			50	ms
t_HV2DEVEN	Wait time from HV_OK High before DEV_EN can be asserted low⁽²⁾	V_{HV_OK} ≥ 1.65 V to V_{DEV_EN} ≤ 1.65 V C_{HV_OK} = 100 pF	2			ms

(1) TBT_IN must transition from 3.3 V to high voltage, not from 0 V to high voltage

(2) During the transition from low voltage input to high voltage input, the total load of all outputs combined can not exceed 85 mA until 2 ms after HV_OK asserts high.

(3) The charge pump will limit the normal ramp of current. Soft start will control the inrush current when the input ramps from 0 V to high voltage (not a normal operating condition). See recommended components section for required soft-start cap.

7.7 Timing Diagrams

Figure 1. TBT_IN Slew Rates

The TPS65980 has two normal operating regions. The first region is when 2.5 V ≤ V_{TBT_IN} ≤ 3.4 V. This is the normal power-up state and is termed the low-voltage state. When the input transitions to this range, the input slew rate must meet the SR_02L limits. In this voltage range, the TPS65980 operates with a charge pump to generate the nominally 3.3 V output. When the input voltage moves to the higher end of this range, the buck converter takes over to produce the 3.3 V. In normal operation, the TPS65980 input voltage will transition from the low-voltage range to a high-voltage range where 10 V ≤ V_{TBT_IN} ≤ 15.75 V. This is the high-voltage state and is the state where the TPS65980 will operate most of the time. In this state, the device operates as a buck converter providing a nominally 3.3 V output. Figure 1 shows the input voltage transitions and states.

Figure 2. Timing Diagram

Figure 2 shows normal operating timing diagram for the TBT_OUT output voltage and the RESET and HV_OK output indicator signals. When TBT_IN transitions to the low-voltage range, TBT_OUT will power up a short time later. Once TBT_OUT reaches the normal output range, RESET will transition high. However, timing for RESET is measured from the input TBT_IN transitioning high. When TBT_IN transitions from the low-voltage input range to the high-voltage input range, HV_OK will transition high. RESET is an active-high output indicating that the TBT_OUT voltage is valid and. HV_OK is an active-high output indicating that the TBT_IN voltage is in the high-voltage range. When in the high-voltage state, the TPS65980 can provide much higher output current than when in the low-voltage state.

When the TBT_IN input transitions from high-voltage to low-voltage, HV_OK will de-assert to a logic low. When the TBT_IN input voltage falls below the minimum operating voltage, the RESET output will de-assert low.

Figure 3. Timing Diagram

Figure 3 shows the CBL_OUT and DEV_OUT outputs and timing based on the HV_OK signal and the DEV_ENZ input. The CBL_OUT output will be connected to TBT_OUT and supplying 3.3V when HV_OK is asserting high. The DEV_OUT output will be connected to TBT_OUT and supplying 3.3 V when HV_OK is asserting high and the DEV_ENZ input is low.

7.8 Typical Characteristics

Figure 4. Low Voltage Efficiency

Figure 6. High Voltage Efficiency (Active)

V_IN = 12V

Figure 8. TBT_OUT Load Regulation

V_IN = 12V

CBL_ILIMIT = 1

Figure 10. CBL_OUT Load Regulation

Figure 12. TBT_OUT Line Regulation

Figure 5. High Voltage Efficiency (System Sleep)

V_IN = 3.3V

Figure 7. TBT_OUT Load Regulation

V_IN= 12V

Figure 9. DEV_OUT Load Regulation

V_IN = 12V

CBL_ILIMIT = 0

Figure 11. CBL_OUT Load Regulation