SLVSER3A November   2018  – April 2020 TPS65982BB

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  Power Supervisor Characteristics
    7. 6.7  Power Consumption Characteristics
    8. 6.8  Port-Power Switch Characteristics
    9. 6.9  Port-Data Multiplexer Characteristics
    10. 6.10 Port-Data Multiplexer Clamp Characteristics
    11. 6.11 Port-Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics
    12. 6.12 USB Endpoint Characteristics
    13. 6.13 Input/Output (I/O) Characteristics
    14. 6.14 I2C Slave Characteristics
    15. 6.15 Thermal Shutdown Characteristics
    16. 6.16 Oscillator Characteristics
    17. 6.17 SPI Master Switching Characteristics
    18. 6.18 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Port-Power Switches
        1. 8.3.1.1 5-V Power Delivery
        2. 8.3.1.2 5-V Power Switch
        3. 8.3.1.3 PP_5V0 Current Limit
        4. 8.3.1.4 VBUS Transition to VSAFE0V
      2. 8.3.2  USB Port-Data Multiplexer
        1. 8.3.2.1 Port Multiplexer Clamp
        2. 8.3.2.2 USB2.0 Low-Speed Endpoint
      3. 8.3.3  Power Management
        1. 8.3.3.1 Power-On and Supervisory Functions
      4. 8.3.4  Digital Core
      5. 8.3.5  Power Reset-Control Module (PRCM)
      6. 8.3.6  Interrupt Monitor
      7. 8.3.7  I2C Slave
      8. 8.3.8  SPI Master
      9. 8.3.9  Thermal Shutdown
      10. 8.3.10 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 SPI Master Interface
      2. 8.4.2 I2C Slave Interface
        1. 8.4.2.1 I2C Interface Description
        2. 8.4.2.2 I2C Clock Stretching
        3. 8.4.2.3 I2C Address Setting
        4. 8.4.2.4 Unique-Address Interface
        5. 8.4.2.5 I2C Pin Address Setting
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 VBUS Load Switch
      2. 9.2.2 HRESET
      3. 9.2.3 Dual Port Billboard Support
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 1VIN_3V3 Input Switch
      2. 10.1.2 VOUT_3V3 Output Switch
    2. 10.2 1.8-V Core Power
      1. 10.2.1 1.8-V Digital LDO
      2. 10.2.2 1.8-V Analog LDO
    3. 10.3 VDDIO
      1. 10.3.1 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement
      2. 11.2.2 Recommended Via Size and Trace Widths
      3. 11.2.3 USB2 Routing
      4. 11.2.4 Oval Pad for BGA Fanout
      5. 11.2.5 Top and Bottom Layer Complete Routing
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

ZBH Package
96-Pin NFBGA
Transparent Top View
TPS65982BB PACKAGE_1_ZBH_bga_pin_diagram.gif

Pin Functions

PIN TYPE POR
STATE		 DESCRIPTION
NAME NO.
PP_5V0 A11, B11, C11, D11 Power — 5-V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused.
VBUS H11, J10, J11, K11 Power — 5-V output from PP_5V0. Bypass with capacitance CVBUS to GND.
VIN_3V3 H1, F10 Power — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
VDDIO B1 Power  — VDD for I/O.
VOUT_3V3 H2 Power — Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused.
LDO_3V3 G1 Power — Output of the VBUS to 3.3 V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power optional external flash memory. Bypass with capacitance CLDO_3V3 to GND.
LDO_1V8A K1 Power — Output of the 3.3-V or 1.8-V LDO for core analog circuits. Bypass with capacitance CLDO_1V8A to GND.
LDO_1V8D A2 Power — Output of the 3.3-V or 1.8-V LDO for core digital circuits. Bypass with capacitance CLDO_1V8D to GND.
LDO_BMC E1 Power — Output of the 1.1V output level LDO. Bypass with capacitance CLDO_BMC to GND.
PA_USB_P K6 Analog I/O Hi-Z Port A USB D+ connection.
PA_USB_N L6 Analog I/O Hi-Z Port A USB D- connection.
PB_USB_P K7 Analog I/O Hi-Z Port B USB D+ connection.
PB_USB_N L7 Analog I/O Hi-Z Port B USB D- connection.
USB_RP_P L5 Analog I/O Hi-Z System-side USB2.0 high-speed connection to port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
USB_RP_N K5 Analog I/O Hi-Z System-side USB2.0 high-speed connection to port multiplexer. Ground pin with between 1-kΩ and 5-MΩ resistance when unused.
SENSE B10 Analog input Analog input Short pin to VBUS.
SENSE A10 Analog input Analog input Short pin to VBUS.
SS H7 Analog output Driven low Soft Start. Tie pin to capacitance CSS to ground.
R_OSC G2 Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC.
PP_5V0_EN G11 Digital I/O Hi-Z Input enable signal for PP_5V0 power path.
CONFIG H6 Analog input Hi-Z Boot Configuration pin. Tie directly to ground.
BB_BOOT_OK K3 Digital I/O Hi-Z Output. Driven high once the TPS65982BB has completed its boot and configuration routines.
BB_EN G10 Digital I/O Hi-Z Input. When driven high enables billboard output on PA_USB_P and PA_USB_N.
BB_SRST L3 Digital I/O Hi-Z Input. When asserted high, initiates a soft reset of the TPS65982BB.
BB_PLUG_PB K2 Digital I/O Hi-Z Input. Signals the TPS65982BB to enable the USB billboard on the PA_USB pins.
BB_PLUG_PA L2 Digital I/O Hi-Z Input. Signals the TPS65982BB to enable the USB billboard on the PB_USB pins.
HRESET D6 Digital Input Hi-Z Active high hardware reset input. Assertion causes a reboot sequence. Ground pin when HRESET functionality will not be used.
I2C_SDA1 D1 Digital I/O Digital input I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_SCL1 D2 Digital I/O Digital input I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_IRQ1Z C1 Digital output Hi-Z I2C port 1 interrupt. Active low. Implement externally as an open drain with a pullup resistance. Float pin when unused.
I2C_SDA2 A5 Digital I/O Digital input I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_SCL2 B5 Digital I/O Digital input I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10-kΩ resistance when used or unused.
I2C_IRQ2Z B6 Digital output Hi-Z I2C port 2 interrupt. Active low. Implement externally as an open drain with a pullup resistance. Float pin when unused.
I2C_ADDR F1 Analog I/O Analog input Sets the I2C address for both I2C ports.
SPI_CLK A3 Digital output Digital input SPI serial clock. Ground pin when unused
SPI_MOSI B4 Digital output Digital input SPI serial master output to slave. Ground pin when unused.
SPI_MISO A4 Digital input Digital input SPI serial master input from slave. This pin is used during boot sequence to determine if the optional flash memory is valid. Refer to the Device Functional Modes section for more details. Ground pin when unused.
SPI_SSZ B3 Digital output Digital input SPI slave select. Ground pin when unused.
GND A1, A6, A7, A8, B7, B8, D5, D8, E4, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8, H4, H5, H8, H10, J1, J2, K4, K8, L1, L4, L8 Ground NA Ground. Connect all balls to ground plane.
NC A9, B2, B9, C2, C10, D7, D10, E2, E10, E11, F2, F4, F11, G4, K9, K10, L9, L10, L11 Blank NA Populated Ball that must remain unconnected.
No Ball C3, C4, C5, C6, C7, C8, C9, D3, D4, D9, E3, E9, F3, F9, G3, G9, H3, H9, J3, J4, J5, J6, J7, J8, J9 Blank NA Unpopulated Ball for A1 marker and unpopulated inner ring.