SLVSER3A November 2018 – April 2020 TPS65982BB
PRODUCTION DATA.
The TPS65982BB device loads any ROM patch, configuration or both from flash memory during the sequence. The SPI master electrical characteristics are defined in SPI Master Switching Characteristics and timing characteristics are defined in Figure 3. The TPS65982BB device is designed to power the flash from LDO_3V3, and therefore pullup resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support a 12-MHz SPI clock frequency. The size of the flash must be at least 24 KB to hold the maximum ROM patch and configuration code outlined in the section. The SPI master of the TPS65982BB device supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on the same cycle as the chip select (SPI_SSZ pin) becomes active. The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_MISO and SPI_MOSI pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 KB. The W25X05CL device or similar is recommended.