JAJSFH6D May   2018  – October 2022 TPS65987D

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Consumption Characteristics
    7. 6.7  Power Switch Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 BC1.2 Characteristics
    11. 6.11 Thermal Shutdown Characteristics
    12. 6.12 Oscillator Characteristics
    13. 6.13 I/O Characteristics
    14. 6.14 PWM Driver Characteristics
    15. 6.15 I2C Requirements and Characteristics
    16. 6.16 SPI Controller Timing Requirements
    17. 6.17 HPD Timing Requirements
    18. 6.18 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
        3. 8.3.2.3 Supply Switch Over
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1 PP_HV Power Switch
          1. 8.3.3.1.1 PP_HV Over Current Clamp
          2. 8.3.3.1.2 PP_HV Over Current Protection
          3. 8.3.3.1.3 PP_HV OVP and UVP
          4. 8.3.3.1.4 PP_HV Reverse Current Protection
        2. 8.3.3.2 Schottky for Current Surge Protection
        3. 8.3.3.3 PP_EXT Power Path Control
        4. 8.3.3.4 PP_CABLE Power Switch
          1. 8.3.3.4.1 PP_CABLE Over Current Protection
          2. 8.3.3.4.2 PP_CABLE Input Good Monitor
        5. 8.3.3.5 VBUS Transition to VSAFE5V
        6. 8.3.3.6 VBUS Transition to VSAFE0V
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a DFP
        2. 8.3.4.2 Configured as a UFP
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Fast Role Swap Signaling
      5. 8.3.5  Dead Battery Operation
        1. 8.3.5.1 Dead Battery Advertisement
        2. 8.3.5.2 BUSPOWER (ADCIN1)
      6. 8.3.6  Battery Charger Detection and Advertisement
        1. 8.3.6.1 BC1.2 Data Contact Detect
        2. 8.3.6.2 BC1.2 Primary and Secondary Detection
        3. 8.3.6.3 Charging Downstream Port Advertisement
        4. 8.3.6.4 Dedicated Charging Port Advertisement
        5. 8.3.6.5 2.7V Divider3 Mode Advertisement
        6. 8.3.6.6 1.2V Mode Advertisement
        7. 8.3.6.7 DCP Auto Mode Advertisement
      7. 8.3.7  ADC
      8. 8.3.8  DisplayPort HPD
      9. 8.3.9  Digital Interfaces
        1. 8.3.9.1 General GPIO
        2. 8.3.9.2 I2C
        3. 8.3.9.3 SPI
      10. 8.3.10 PWM Driver
      11. 8.3.11 Digital Core
      12. 8.3.12 I2C Interfaces
        1. 8.3.12.1 I2C Interface Description
        2. 8.3.12.2 I2C Clock Stretching
        3. 8.3.12.3 I2C Address Setting
        4. 8.3.12.4 Unique Address Interface
        5. 8.3.12.5 I2C Pin Address Setting (ADCIN2)
      13. 8.3.13 SPI Controller Interface
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot
      2. 8.4.2 Power States
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Type-C VBUS Design Considerations
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Type-C Connector VBUS Capacitors
          2. 9.2.1.2.2 VBUS Schottky and TVS Diodes
          3. 9.2.1.2.3 VBUS Snubber Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Notebook Design Supporting PD Charging
        1. 9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging
          1. 9.2.2.1.1 Design Requirements
          2. 9.2.2.1.2 Detailed Design Procedure
            1. 9.2.2.1.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.1.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.1.2.3 USB and DisplayPort Supported Data Modes
            4. 9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control
        2. 9.2.2.2 Thunderbolt Notebook Supporting PD Charging
          1. 9.2.2.2.1 Design Requirements
          2. 9.2.2.2.2 Detailed Design Procedure
            1. 9.2.2.2.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.2.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.2.2.3 Thunderbolt Supported Data Modes
            4. 9.2.2.2.2.4 RESETN
            5. 9.2.2.2.2.5 I2C Design Requirements
            6. 9.2.2.2.2.6 TS3DS10224 SBU Mux for AUX and LSTX/RX
            7. 9.2.2.2.2.7 Thunderbolt Flash Options
        3. 9.2.2.3 USB and DisplayPort Dock with Bus-Powered and Self-Powered Support
          1. 9.2.2.3.1 Design Requirements
          2. 9.2.2.3.2 Detailed Design Procedure
            1. 9.2.2.3.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.3.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.3.2.3 USB and DisplayPort Supported Data Modes
            4. 9.2.2.3.2.4 TUSB1064 Super Speed Mux GPIO Control
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VBUS 3.3-V LDO
    2. 10.2 1.8-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Top TPS65987D Placement and Bottom Component Placement and Layout
    2. 11.2 Layout Example
    3. 11.3 Component Placement
    4. 11.4 Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3, LDO_3V3, LDO_1V8
    5. 11.5 Routing CC and GPIO
    6. 11.6 Thermal Dissipation for FET Drain Pads
    7. 11.7 USB2 Recommended Routing For BC1.2 Detection/Advertisement
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Firmware Warranty Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Power Switch Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
RPPCCPP_CABLE to C_CCn power switch resistance4.7 ≤ PP_CABLE ≤ 5.5222325
2.95 ≤ PP_CABLE < 4.7269414
RPPHVPP_HVx to VBUSx power switch resistanceTj = 25C2533
IPPHVContinuous current capabillity of power path from PP_HVx to VBUSx5A
IPPCCContinuous current capabillity of power path from PP_CABLE to C_CCnTJ = 125C320mA
TJ = 85C600mA
IHVACTActive quiescent current from PP_HV pin, EN_HV = 1Source Configuration, Comparator RCP function enabled, ILOAD = 100mA1mA
IHVSDShutdown quiescent current from PP_HV pin, EN_HV = 0VPPHV = 20V100µA
IOCCOver Current Clamp Firmware Selectable Settings1.1401.2671.393A
1.3801.5331.687A
1.6201.8001.980A
1.8602.0672.273A
2.1002.3332.567A
2.342.6002.860A
2.5802.8673.153A
2.8203.1333.447A
3.0603.4003.74A
3.3003.6674.033A
3.5403.9334.327A
3.7804.2004.620A
4.0204.4674.913A
4.2604.7335.207A
4.5005.005.500A
4.7405.2675.793A
4.9805.5336.087A
5.2205.8006.380A
5.4606.0676.673A
5.6976.3306.963A
IOCPPP_HV Quick Response Current Limit10A
ILIMPPCCPP_CABLE current limit0.60.750.9A
IHV_ACC 1PP_HV current sense accuracyI = 100 mA, Reverse current blocking disabled3.968.1A/V
IHV_ACC 1PP_HV current sense accuracyI = 200 mA4.867.2A/V
IHV_ACC 1PP_HV current sense accuracyI = 500 mA5.2866.72A/V
IHV_ACC 1PP_HV current sense accuracyI ≥ 1 A5.466.6A/V
tON_HVPP_HV path turn on time from enable to VBUS = 95% of PP_HV voltageConfigured as a source or as a sink with soft start disabled. PP_HV = 20 V, CVBUS = 10 µF, ILOAD = 100 mA8ms
tON_FRSPP_HV path turn on time from enable to VBUS = 95% of PP_HV voltage during an FRS enableConfigured as a source. PP_HV = 5 V, CVBUS = 10 µF, ILOAD = 100 mA150μs
tON_CCPP_CABLE path turn on time from enable to C_CCn = 95% of the PP_CABLE voltagePP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA2ms
SSConfigurable soft start slew rate for sink configurationILOAD = 100mA, setting 00.2700.4090.45V/ms
ILOAD = 100mA, setting 10.60.7871V/ms
ILOAD = 100mA, setting 21.21.5671.7V/ms
ILOAD = 100mA, setting 32.33.3883.6V/ms
VREVPHVReverse current blocking voltage threshold for PP_HV switchDiode Mode610mV
Comparator Mode36mV
VSAFE0VVoltage that is a safe 0 V per USB-PD specification00.8V
tSAFE0VVoltage transition time to VSAFE0V650ms
SRPOSMaximum slew rate for positive voltage transitions0.03V/µs
SRNEGMaximum slew rate for negative voltage transitions–0.03V/µs
tSTABLEEN to stable time for both positive and negative voltage transitions275ms
VSRCVALIDSupply output tolerance beyond VSRCNEW during time tSTABLE–0.50.5V
VSRCNEWSupply output tolerance–55%
tVCONNDISTime from cable detach to VVCONNDIS250ms
VVCONNDISVoltage at which VCONN is considered discharged150mV