JAJSFH6D May   2018  – October 2022 TPS65987D

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Requirements and Characteristics
    6. 6.6  Power Consumption Characteristics
    7. 6.7  Power Switch Characteristics
    8. 6.8  Cable Detection Characteristics
    9. 6.9  USB-PD Baseband Signal Requirements and Characteristics
    10. 6.10 BC1.2 Characteristics
    11. 6.11 Thermal Shutdown Characteristics
    12. 6.12 Oscillator Characteristics
    13. 6.13 I/O Characteristics
    14. 6.14 PWM Driver Characteristics
    15. 6.15 I2C Requirements and Characteristics
    16. 6.16 SPI Controller Timing Requirements
    17. 6.17 HPD Timing Requirements
    18. 6.18 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
        3. 8.3.2.3 Supply Switch Over
      3. 8.3.3  Port Power Switches
        1. 8.3.3.1 PP_HV Power Switch
          1. 8.3.3.1.1 PP_HV Over Current Clamp
          2. 8.3.3.1.2 PP_HV Over Current Protection
          3. 8.3.3.1.3 PP_HV OVP and UVP
          4. 8.3.3.1.4 PP_HV Reverse Current Protection
        2. 8.3.3.2 Schottky for Current Surge Protection
        3. 8.3.3.3 PP_EXT Power Path Control
        4. 8.3.3.4 PP_CABLE Power Switch
          1. 8.3.3.4.1 PP_CABLE Over Current Protection
          2. 8.3.3.4.2 PP_CABLE Input Good Monitor
        5. 8.3.3.5 VBUS Transition to VSAFE5V
        6. 8.3.3.6 VBUS Transition to VSAFE0V
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a DFP
        2. 8.3.4.2 Configured as a UFP
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Fast Role Swap Signaling
      5. 8.3.5  Dead Battery Operation
        1. 8.3.5.1 Dead Battery Advertisement
        2. 8.3.5.2 BUSPOWER (ADCIN1)
      6. 8.3.6  Battery Charger Detection and Advertisement
        1. 8.3.6.1 BC1.2 Data Contact Detect
        2. 8.3.6.2 BC1.2 Primary and Secondary Detection
        3. 8.3.6.3 Charging Downstream Port Advertisement
        4. 8.3.6.4 Dedicated Charging Port Advertisement
        5. 8.3.6.5 2.7V Divider3 Mode Advertisement
        6. 8.3.6.6 1.2V Mode Advertisement
        7. 8.3.6.7 DCP Auto Mode Advertisement
      7. 8.3.7  ADC
      8. 8.3.8  DisplayPort HPD
      9. 8.3.9  Digital Interfaces
        1. 8.3.9.1 General GPIO
        2. 8.3.9.2 I2C
        3. 8.3.9.3 SPI
      10. 8.3.10 PWM Driver
      11. 8.3.11 Digital Core
      12. 8.3.12 I2C Interfaces
        1. 8.3.12.1 I2C Interface Description
        2. 8.3.12.2 I2C Clock Stretching
        3. 8.3.12.3 I2C Address Setting
        4. 8.3.12.4 Unique Address Interface
        5. 8.3.12.5 I2C Pin Address Setting (ADCIN2)
      13. 8.3.13 SPI Controller Interface
      14. 8.3.14 Thermal Shutdown
      15. 8.3.15 Oscillators
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boot
      2. 8.4.2 Power States
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Type-C VBUS Design Considerations
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Type-C Connector VBUS Capacitors
          2. 9.2.1.2.2 VBUS Schottky and TVS Diodes
          3. 9.2.1.2.3 VBUS Snubber Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Notebook Design Supporting PD Charging
        1. 9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging
          1. 9.2.2.1.1 Design Requirements
          2. 9.2.2.1.2 Detailed Design Procedure
            1. 9.2.2.1.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.1.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.1.2.3 USB and DisplayPort Supported Data Modes
            4. 9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control
        2. 9.2.2.2 Thunderbolt Notebook Supporting PD Charging
          1. 9.2.2.2.1 Design Requirements
          2. 9.2.2.2.2 Detailed Design Procedure
            1. 9.2.2.2.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.2.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.2.2.3 Thunderbolt Supported Data Modes
            4. 9.2.2.2.2.4 RESETN
            5. 9.2.2.2.2.5 I2C Design Requirements
            6. 9.2.2.2.2.6 TS3DS10224 SBU Mux for AUX and LSTX/RX
            7. 9.2.2.2.2.7 Thunderbolt Flash Options
        3. 9.2.2.3 USB and DisplayPort Dock with Bus-Powered and Self-Powered Support
          1. 9.2.2.3.1 Design Requirements
          2. 9.2.2.3.2 Detailed Design Procedure
            1. 9.2.2.3.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.3.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.3.2.3 USB and DisplayPort Supported Data Modes
            4. 9.2.2.3.2.4 TUSB1064 Super Speed Mux GPIO Control
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VBUS 3.3-V LDO
    2. 10.2 1.8-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Top TPS65987D Placement and Bottom Component Placement and Layout
    2. 11.2 Layout Example
    3. 11.3 Component Placement
    4. 11.4 Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3, LDO_3V3, LDO_1V8
    5. 11.5 Routing CC and GPIO
    6. 11.6 Thermal Dissipation for FET Drain Pads
    7. 11.7 USB2 Recommended Routing For BC1.2 Detection/Advertisement
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Firmware Warranty Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 Boot

At initial power on the device goes through a boot routine. This routine is responsible for initializing device register values and loading device patch and configuration bundles. The device's functional behavior after boot can be configured through the use of pin straps on the SPI_POCI and ADCIN1 pins as shown in Table 8-5.

Table 8-5 Boot Mode Pin Strapping
SPI_POCIADCIN1
DIV = R2/(R1+R2)(1)		Dead Battery ModeDevice Configuration
DIV MINDIV MAX
10.000.18BP_NoResponseSafe Configuration
10.200.28BP_WaitFor3V3_InternalSafe Configuration
10.300.38BP_ECWait_InternalInfinite Wait
10.400.48BP_WaitFor3V3_ExternalSafe Configuration
10.500.58BP_ECWait_ExternalInfinite Wait
10.601.00BP_NoWaitSafe Configuration
00.100.18BP_NoResponseConfiguration 1
00.200.28BP_NoWaitConfiguration 2
00.300.38BP_ECWait_InternalInfinite Wait
00.400.48BP_NoWaitConfiguration 3
00.500.58BP_ECWait_ExternalInfinite Wait
00.600.68BP_NoWaitConfiguration 4
00.700.78BP_NoWaitReserved
00.800.88BP_NoResponseReserved
00.901.00BP_NoWaitConfiguration 5
(1) External resistor tolerance of 1% is required. Resistor values must be chosen to yield a DIV value centered nominally between listed MIN and MAX values.

The pin strapping configures two different parameters, Dead battery mode and device configuration. The dead battery mode selects device behavior when powered from VBUS. The dead battery mode behaviors are detailed in Table 8-6.

Table 8-6 Dead Battery Configurations
CONFIGURATIONDESCRIPTION
BP_NoResponseNo power switch is enabled and the device does not start-up until VIN_3V3 is present
BP_WaitFor3V3_InternalThe internal power switch from VBUSx to PP_HVx is enabled for the port receiving power. The device does not continue to start-up or attempt to load device configurations until VIN_3V3 is present.
BP_WaitFor3V3_ExternalThe external power switch from VBUSx to PP_HVx is enabled for the port receiving power. The device does not continue to start-up or attempt to load device configurations until VIN_3V3 is present.
BP_ECWait_InternalThe internal power switch from VBUSx to PP_HVx is enabled for the port receiving power. The device infinitely tries to load configuration.
BP_ECWait_ExternalThe external power switch from VBUSx to PP_HVx is enabled for the port receiving power. The device infinitely tries to load configuration.
BP_NoWaitThe device continues to start-up and attempts to load configurations while receiving power from VBUS. Once configuration is loaded the appropriate power switch is closed based on the loaded configuration.
Note:

Devices implementing the BP_WaitFor3V3_External or BP_ECWait_External configuration must use GPIO16 for external sink path control, while devices implementing the BP_WaitFor3V3_Internal or BP_ECWait_Internal must use PPHV1 as the sink path.

When powering up from VIN_3V3 or VBUS the device will attempt to load configuration information from the SPI or I2C digital interfaces. The device configuration settings select the device behavior should configuration information not be available during the device boot process. Table 8-7 shows the device behavior for each device configuration setting.

Table 8-7 Device Default Configurations
ConfigurationDescription
SafePorts disabled, if powered from VBUS operates a legacy sink
Infinite WaitDevice infinitely waits in boot state for configuration information
Configuration 1DFP only (Internal Switch)
5 V at 3 A Source capability
TBT Alternate Modes not enabled
DisplayPort Alternate Mode not enabled (DFP_D, C/D/E)
Configuration 2UFP only (Internal Switch)
5 V at 0.9 - 3.0 A Sink capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
Configuration 3UFP only (Internal Switch)
5-20 V at 0.9 - 3.0 A Sink capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
Configuration 4UFP only (External Switch)
5 V at 0.9-3.0 A Sink capability
5 V at 3.0 A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported
Configuration 5UFP only (External Switch))
5-20 V at 0.9-3.0 A Sink capability
5 V at 3.0 A Source capability
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported