JAJSJT6A August   2020  – July 2021 TPS65994AD

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PP_5V Power Switch Characteristics
    9. 6.9  PP_EXT Power Switch Characteristics
    10. 6.10 Power Path Supervisory
    11. 6.11 CC Cable Detection Parameters
    12. 6.12 CC VCONN Parameters
    13. 6.13 CC PHY Parameters
    14. 6.14 Thermal Shutdown Characteristics
    15. 6.15 ADC Characteristics
    16. 6.16 Input/Output (I/O) Characteristics
    17. 6.17 I2C Requirements and Characteristics
    18. 6.18 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.1.4 USB-PD BMC Transmitter
        5. 8.3.1.5 USB-PD BMC Receiver
        6. 8.3.1.6 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 Internal Sourcing Power Paths
          1. 8.3.3.1.1  PP_5Vx Current Clamping
          2. 8.3.3.1.2  PP_5Vx Local Overtemperature Shut Down (OTSD)
          3. 8.3.3.1.3  PP_5Vx Current Sense
          4. 8.3.3.1.4  PP_5Vx OVP
          5. 8.3.3.1.5  PP_5Vx UVLO
          6. 8.3.3.1.6  PP_5Vx Reverse Current Protection
          7. 8.3.3.1.7  Fast Role Swap
          8. 8.3.3.1.8  PP_CABLE Current Clamp
          9. 8.3.3.1.9  PP_CABLE Local Overtemperature Shut Down (OTSD)
          10. 8.3.3.1.10 PP_CABLE UVLO
        2. 8.3.3.2 Sink Path Control
          1. 8.3.3.2.1 Overvoltage Protection (OVP)
          2. 8.3.3.2.2 Reverse-Current Protection (RCP)
          3. 8.3.3.2.3 VBUS UVLO
          4. 8.3.3.2.4 Discharging VBUS to Safe Voltage
      4. 8.3.4  Cable Plug and Orientation Detection
        1. 8.3.4.1 Configured as a Source
        2. 8.3.4.2 Configured as a Sink
        3. 8.3.4.3 Configured as a DRP
        4. 8.3.4.4 Fast Role Swap Signal Detection
        5. 8.3.4.5 Dead Battery Advertisement
      5. 8.3.5  Default Behavior Configuration (ADCIN1, ADCIN2)
      6. 8.3.6  ADC
      7. 8.3.7  DisplayPort Hot-Plug Detect (HPD)
      8. 8.3.8  Digital Interfaces
        1. 8.3.8.1 General GPIO
        2. 8.3.8.2 I2C Interface
      9. 8.3.9  Digital Core
      10. 8.3.10 I2C Interface
        1. 8.3.10.1 I2C Interface Description
        2. 8.3.10.2 I2C Clock Stretching
        3. 8.3.10.3 I2C Address Setting
        4. 8.3.10.4 Unique Address Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Strapping to Configure Default Behavior
      2. 8.4.2 Power States
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Type-C VBUS Design Considerations
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Type-C Connector VBUS Capacitors
          2. 9.2.1.2.2 VBUS Schottky and TVS Diodes
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Notebook Design Supporting PD Charging
        1. 9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging
          1. 9.2.2.1.1 Design Requirements
          2. 9.2.2.1.2 Detailed Design Procedure
            1. 9.2.2.1.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.1.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.1.2.3 USB and DisplayPort Supported Data Modes
            4. 9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control
        2. 9.2.2.2 Thunderbolt Notebook Supporting PD Charging
          1. 9.2.2.2.1 Design Requirements
          2. 9.2.2.2.2 Detailed Design Procedure
            1. 9.2.2.2.2.1 USB Power Delivery Source Capabilities
            2. 9.2.2.2.2.2 USB Power Delivery Sink Capabilities
            3. 9.2.2.2.2.3 Thunderbolt Supported Data Modes
            4. 9.2.2.2.2.4 I2C Design Requirements
            5. 9.2.2.2.2.5 TS3DS10224 SBU Mux for AUX and LSTX/RX
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V Power
      1. 10.1.1 VIN_3V3 Input Switch
      2. 10.1.2 VBUS 3.3-V LDO
    2. 10.2 1.5-V Power
    3. 10.3 Recommended Supply Load Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Top TPS65994AD Placement and Bottom Component Placement and Layout
    2. 11.2 Layout Example
    3. 11.3 Component Placement
    4. 11.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3, LDO_1V5
    5. 11.5 Routing CC and GPIO
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 PP_EXT Power Switch Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPx_GATE_ON Gate driver sourcing current 0 ≤ VPx_GATE_VSYS-VVSYS ≤ 6 V, 0 V ≤ VVSYS ≤ 22 V, VPx_VBUS > 4 V, measure IPx_GATE_VSYS 8.5 10 11.5 µA
0 ≤ VPx_GATE_VBUS-VPx_VBUS ≤ 6 V, 4 V ≤ VPx_VBUS ≤ 22 V, measure IPx_GATE_VBUS 8.5 10 11.5 µA
VPx_GATE_ON sourcing voltage (ON) 0 ≤ VVSYS ≤ 22 V, IPx_GATE_VSYS < 4 µA, measure VPx_GATE_VSYS – VVSYS, VPx_VBUS > 4 V. 6 12 V
4 V ≤ VPx_VBUS ≤ 22 V, IPx_GATE_VBUS < 4 µA, measure VPx_GATE_VBUS – VPx_VBUS. 6 12 V
VRCP comparator mode RCP threshold, VVSYS - VPx_VBUS. setting 0, 4 V ≤ VPx_VBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV
setting 1, 4 V ≤ VPx_VBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV
setting 2, 4 V ≤ VPx_VBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV
setting 3, 4 V ≤ VPx_VBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV
IPx_GATE_OFF Sinking strength normal turnoff: VVSYS = 5V, VPx_GATE_VSYS=6V 13 µA
normal turnoff: VPx_VBUS = 5V, VPx_GATE_VBUS=6V, VVSYS = 5 V 13 µA
RPx_GATE_FSD Sinking strength fast turnoff: VVSYS = 5V, VPx_GATE_VSYS=6V, 85 Ω
fast turnoff: VPx_VBUS = 5V, VPx_GATE_VBUS=6V, VVSYS = 5 V 85 Ω
RPx_GATE_OFF_UVLO Sinking strength in UVLO (safety) VVIN_3V3=0V, VPx_VBUS=3.0V, VPx_GATE_VSYS=0.1V 1.5 MΩ
SS soft start slew rate for Px_GATE_VSYS, setting 0 4 V ≤ VPx_VBUS ≤ 22 V, 500pF < CPx_GATE_VSYS < 16 nF, measure slope from 10% to 90% of final Px_GATE_VSYS value,   0.35 0.47 V/ms
soft start slew rate for Px_GATE_VSYS, setting 1 0.67 0.91
soft start slew rate for Px_GATE_VSYS, setting 2 1.33 1.83
soft start slew rate for Px_GATE_VSYS, setting 3 2.88 3.90
tPx_GATE_VBUS_OFF Time allowed to disable the external
FET via Px_GATE_VBUS in normal
shutdown mode.(1) 		VPx_VBUS=20V, Gate is off when VGS < 1 V 260 µs
tPx_GATE_VBUS_OVP Time allowed to disable the external
FET via Px_GATE_VBUS in fast
shutdown mode (VOVP4RCP exceeded).(1) 		OVP: VOVP4RCP= setting 57, VPx_VBUS=20V initially, then raised to 23V in 50ns, Gate is off when VGS < 1 V 3 µs
tPx_GATE_VBUS_RCP Time allowed to disable the external
FET via Px_GATE_VBUS in fast
shutdown mode (VRCP exceeded).(1) 		RCP: VRCP= setting 0, VPx_VBUS=5V, VVSYS=5V initially, then raised to 5.5V in 50ns, Gate is off when VGS < 1 V 1.2 µs
tPx_GATE_VSYS_OFF Time allowed to disable the external FET via Px_GATE_VSYS in normal shutdown mode(1) VVSYS=20V, Gate is off when VGS < 1 V 0.25 ms
tPx_GATE_VSYS_FSD Time allowed to disable the external FET via Px_GATE_VSYS in fast shutdown mode (OVP or FRS)(1) VVSYS=VVBUS=20V initially, then VVBUS raised to 23V in 50ns, Gate is off when VGS< 1 V 0.25 μs
tPx_GATE_VBUS_ON time to enable Px_GATE_VBUS (1) measure time from when VGS=0V until VGS>3V 0.25 ms
(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.