JAJS384D December   2008  – November 2023 TPS714

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Supply Current
      3. 6.3.3 Current Limit
      4. 6.3.4 Dropout Voltage (VDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS71401 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20230911-SS0I-NN4C-HH6N-8LJHZDSTTJDF-low.svgFigure 4-1 DRV Package,6-Pin WSON(Top View)
GUID-20230911-SS0I-X0H1-L8MC-SDW7T60LZRRZ-low.svgFigure 4-2 DCK Package,5-Pin SC70(Top View)
Pin Functions
TPS714 DESCRIPTION
NAME DCK DRV
FIXED ADJ. FIXED ADJ.
FB — 1 — 4 In the adjustable configuration, this pin sets the output voltage with the help of the external feedback divider.
GND 2 2 3, Pad 3, Pad Ground pin.
NC 1,3 3 2, 4, 5 2, 5 No connect pin. This pin is not connected internally. Connect this pin to ground for best thermal performance or leave floating.
IN 4 4 1 1 Input supply pin. Use a capacitor with a value of 0.1 µF or larger from this pin to ground.(2) See the Input and Output Capacitor Requirements section for more information.
OUT 5 5 6 6 Output of the regulator. For the new chip, a capacitor with a value of 1 µF or larger is required from this pin to ground.(1) See the Input and Output Capacitor Requirements section for more information.
(1) The nominal output capacitance must be greater than 0.47 µF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 0.47 µF. The legacy chip is stable for any capacitor value ≥ 0.47 μF.
(2) For the legacy chip, use a capacitor with a value of 0.047 µF or larger from IN to ground.