JAJS384D December   2008  – November 2023 TPS714

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Supply Current
      3. 6.3.3 Current Limit
      4. 6.3.4 Dropout Voltage (VDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS71401 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.3 Application Curves

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)

GUID-2A9A49F6-4900-4EB1-8776-9F20C084C4DF-low.gif
 
Figure 7-4 Power-Up and Power-Down (Legacy Chip)
GUID-20231024-SS0I-VHMP-CMHZ-L2QRTBZCWRKC-low.svg
 
Figure 7-6 TPS71433 Fast Power-Up (Legacy Chip)
GUID-F62AAD8C-E40B-438B-986E-742A1BBA7D78-low.gif
 
Figure 7-8 Line Transient Response (Legacy Chip)
GUID-ACFAA30F-4CCF-4AA8-A294-7CD47093848F-low.gif
 
Figure 7-10 Load Transient Response (Legacy Chip)
GUID-20221102-SS0I-B4GQ-6TJF-CRBC8XMFB4WG-low.svg
 
Figure 7-5 Power-Up and Power-Down (New Chip)
GUID-20231024-SS0I-357Q-BR79-QXJZMZVGR0KL-low.svg
 
Figure 7-7 TPS71433 Fast Power-Up (New Chip)
GUID-20221102-SS0I-STC9-WDQG-PZ7JJBZPHKLR-low.svg
 
Figure 7-9 Line Transient Response (New Chip)
GUID-20231024-SS0I-LRBR-C3CX-S44T98HWD7GD-low.svg
 
Figure 7-11 Load Transient Response (New Chip)