JAJS384D December   2008  – November 2023 TPS714

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Wide Supply Range
      2. 6.3.2 Low Supply Current
      3. 6.3.3 Current Limit
      4. 6.3.4 Dropout Voltage (VDO)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting VOUT for the TPS71401 Adjustable LDO
        2. 7.2.2.2 External Capacitor Requirements
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.0 V or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)

GUID-B2B74855-209F-4BAC-8126-0868D217F46D-low.gif
 
Figure 5-1 TPS71433 Output Voltage vs Output Current
(Legacy Chip)
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Figure 5-3 TPS71433 Output Voltage vs Input Voltage
(New Chip)
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Figure 5-5 TPS71433 Output Voltage vs Junction Temperature (New Chip)
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Figure 5-7 TPS71433 Quiescent Current vs Junction Temperature (New Chip)
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Figure 5-9 TPS71433 Quiescent Current vs Load Current
(New Chip)
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Figure 5-11 TPS71433 Dropout Voltage vs Output Current
(New Chip)
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Figure 5-13 TPS71433 Dropout Voltage vs Junction Temperature (New Chip)
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Figure 5-15 TPS71433 Output Spectral Noise Density vs Frequency (Legacy Chip)
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Figure 5-17 TPS71433 Output Impedance vs Frequency (Legacy Chip)
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Figure 5-19 TPS71433 VOUT vs Current Limit (New Chip)
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Figure 5-21 TPS71433 Power-Supply Ripple Rejection vs Frequency (Legacy Chip)
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Figure 5-23 TPS71433 Power-Up, Power-Down (Legacy Chip)
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Figure 5-25 TPS71433 Fast Power-Up (Legacy Chip)
GUID-E0CD92F5-A984-4DC1-AA55-827064C2AD3D-low.gif
 
Figure 5-27 TPS71433 Line Transient Response (Legacy Chip)
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Figure 5-29 TPS71433 Load Transient Response (Legacy Chip)
GUID-20231024-SS0I-QSN1-PJWJ-5QHLFRWTLK9Z-low.svg
 
Figure 5-2 TPS71433 Output Voltage vs Output Current
(New Chip)
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Figure 5-4 TPS71433 Output Voltage vs Junction Temperature (Legacy Chip)
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Figure 5-6 TPS71433 Quiescent Current vs Junction Temperature (Legacy Chip)
GUID-20231024-SS0I-BHTS-B8W4-CK8NS1WCF3FG-low.svg
 
Figure 5-8 TPS71433 Quiescent Current vs Input Voltage
(New Chip)
GUID-A5F28EF5-80BA-4A11-89F1-4EF44A5C9F8C-low.gif
 
Figure 5-10 TPS71433 Dropout Voltage vs Output Current (Legacy Chip)
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Figure 5-12 TPS71433 Dropout Voltage vs Junction Temperature (Legacy Chip)
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Figure 5-14 TPS71401 Dropout Voltage vs Input Voltage
(New Chip)
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Figure 5-16 TPS71433 Output Spectral Noise Density vs Frequency (New Chip)
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Figure 5-18 TPS71433 VOUT vs Current Limit (Legacy Chip)
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Figure 5-20 TPS71433 Current Limit vs Junction Temperature (New Chip)
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Figure 5-22 TPS71433 Power-Supply Ripple Rejection vs Frequency (New Chip)
GUID-20221031-SS0I-SGTH-4LDN-CLLF5TDZ0GKX-low.svg
 
Figure 5-24 TPS71433 Power-Up, Power-Down (New Chip)
GUID-20231024-SS0I-357Q-BR79-QXJZMZVGR0KL-low.svg
 
Figure 5-26 TPS71433 Fast Power-Up (New Chip)
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Figure 5-28 TPS71433 Line Transient Response (New Chip)
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Figure 5-30 TPS71433 Load Transient Response (New Chip)