JAJS385T May   2001  – December 2022 TPS715

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 6.4 Electrical Characteristics
    6. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Wide Supply Range
      2. 7.3.2 Low Quiescent Current
      3. 7.3.3 Dropout Voltage (VDO)
      4. 7.3.4 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Setting VOUT for the TPS71501 Adjustable LDO
        2. 8.2.1.2 External Capacitor Requirements
        3. 8.2.1.3 Input and Output Capacitor Requirements
        4. 8.2.1.4 Reverse Current
        5. 8.2.1.5 Feed-Forward Capacitor (CFF)
        6. 8.2.1.6 Power Dissipation (PD)
        7. 8.2.1.7 Estimating Junction Temperature
      2. 8.2.2 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Power Dissipation
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage (1) IO = 10 mA 2.5 24 V
IO = 50 mA 3 24
VOUT Output voltage range (TPS71501)  1.205 15 V
Output voltage accuracy (1)(2) VOUT + 1 V ≤ VIN ≤ 24 V,
100 µA ≤ IOUT ≤ 50 mA		 –4 4 %
IGND Ground pin current (legacy chip)(3) 0 ≤ IOUT ≤ 50 mA , TJ = –40°C to 85°C 3.2 4.2 μA
0 mA ≤ IOUT ≤ 50 mA  3.2 4.8
0 mA ≤ IOUT ≤ 50 mA , VIN = 24 V 5.8
Ground pin current (new chip) (3) 0 ≤ IOUT ≤ 50 mA , TJ = –40°C to 85°C 3.2 4.1
0 mA ≤ IOUT ≤ 50 mA  3.2 4.3
0 mA ≤ IOUT ≤ 50 mA , VIN = 24 V 4.5
ΔVOUT(ΔIOUT) Load regulation IOUT = 100 μA to 50 mA 22 mV
ΔVOUT(ΔVIN) Output voltage line regulation (legacy chip)  (1) VOUT(NOM) + 1 V ≤ VIN ≤ 24 V 20 60 mV
Output voltage line regulation (new chip)  (1) VOUT(NOM) + 1 V ≤ VIN ≤ 24 V 20 22
Vn Output noise voltage (legacy chip) (4)  BW = 200 Hz to 100 kHz,
COUT = 10 μF, IOUT = 50 mA		 575 μVrms
Output noise voltage (new chip)(4)  BW = 200 Hz to 100 kHz,
COUT = 10 μF, IOUT = 50 mA		 425
ICL Output current limit (legacy chip) VOUT = 0 V, VIN ≥ 3.5 V 125 750 mA
VOUT = 0 V, VIN < 3.5 V 90 750
Output current limit (new chip) VOUT = 0 V, VIN ≥ 3.5 V 125 350
VOUT = 0 V, VIN < 3.5 V 90 350
PSRR Power-supply ripple rejection f = 100 kHz, COUT = 10 μF 60 dB
VDO Dropout voltage (legacy chip) IOUT = 50 mA, VIN = VOUT(nom) – 0.1 V 415 750 mV
Dropout voltage (new chip) 415 525
(1) Minimum VIN = VOUT + VDO or the value shown for Input voltage in this table, whichever is greater.
(2) For adjustable device, output accuracy excludes the tolerance and mismatch associated with external resistors used for setting up the output voltage level.
(3) This device employs a leakage null control circuit. This circuit is active only if output current is less than pass FET leakage current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die temperature is greater than 100°C.
(4) See Device Nomenclature for details about new and legacy chip descriptions