SBVS128F June   2009  – December 2015 TPS727

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Soft Start
      3. 7.3.3 Shutdown
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Undervoltage Lock-out (UVLO)
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with EN Control
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input and Output Capacitor Requirements
        2. 8.2.1.2 Transient Response
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Power Dissipation
      3. 10.1.3 Package Mounting
    2. 10.2 Layout Example
      1. 10.2.1 DSE EVM Board Layout
      2. 10.2.2 YFF EVM Board Layout
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Device Nomenclature
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS727 family of low-dropout (LDO) linear regulators are utralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications.

8.2 Typical Application

TPS727 sch_lvu323.gif Figure 25. TPS72718YFF 2.5 VIN to 1.8 VOUT at 200 mA Schematic

8.2.1 Design Requirements

8.2.1.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.

The TPS727 is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 200 mΩ.

8.2.1.2 Transient Response

As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but increases duration of the transient response.

8.2.2 Detailed Design Procedure

Select the desired device based on the output voltage.

Provide an input supply with adequate headroom to include dropout and output current to account for the GND pin current and to power the load.

Select adequate input and output capacitors.

The startup current is given by Equation 2:

Equation 2. TPS727 q_iinrush_lim_bvs128.gif

Equation 2 shows that soft-start current is directly proportional to COUT.

The output voltage ramp rate is independent of COUT and load current and has a typical value of 0.07 V/μs.

The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA, the current that charges the output capacitor.

If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output capacitor and supplying the load current.

If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF × 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA.

8.2.3 Application Curves

TPS727 tc_psrr_fqcy_23v_bvs128.gif
Figure 26. PSRR vs Frequency
(VIN – VOUT = 0.5 V, TPS72718)
TPS727 tc_load_tr_01_bvs128.gif
VIN = 2.3 V, tR = tF = 1 µs
Figure 28. Load Transient Response: 0.1 mA to 200 mA
(TPS72718)
TPS727 tc_load_tr_03_bvs128.gif
VIN = 2.3 V, tR = tF = 1 µs
Figure 30. Load Transient Response: 10 mA to 200 mA
(TPS72718)
TPS727 tc_line_tr_200_bvs128.gif
Slew rate = 1 V/µs, IOUT = 200 µA
Figure 32. Line Transient Response (TPS72718)
TPS727 tc_v_inrush_200_bvs128.gif
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA
Figure 34. VIN Inrush Current (TPS72718)
TPS727 tc_nsd_fqcy_bvs128.gif
IOUT = 10 mA, CIN = COUT = 1 µF
Figure 27. Output Spectral Noise Density vs Output Voltage (TPS72718)
TPS727 tc_load_tr_02_bvs128.gif
VIN = 2.3 V, tR = tF = 1 µs
Figure 29. Load Transient Response: 1 mA to 200 mA (TPS72718)
TPS727 tc_line_tr_100_bvs128.gif
Slew rate = 1 V/µs, IOUT = 100 µA
Figure 31. Line Transient Response (TPS72718)
TPS727 tc_v_inrush_100_bvs128.gif
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA
Figure 33. VIN Inrush Current (TPS72718)
TPS727 tc_v_ramp_up_down_bvs128.gif
IOUT = 200 mA
Figure 35. VIN Ramp Up, Ramp Down Response (TPS72718)

8.3 Do's and Don'ts

Do place at least one 1.0-µF ceramic capacitor as close as possible to the OUT pin of the regulator.

Do not place the output capacitor more than 10 mm away from the regulator.

For DSE devices, do tie the NC pins to ground to improve thermal dissipation.

Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator.

Do not exceed the absolute maximum ratings.