Table 1. Standard 1% Resistor Values for Common Output Voltages

7.3.1 Internal Current Limit

The TPS736xx-Q1 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when V_OUT drops below 0.5 V (see Figure 10). Approximately –0.2 V of V_OUT results in a current limit of 0 mA. Therefore, if OUT is forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS736xx-Q1 must be enabled first.

7.3.2 Transient Response

The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value of 1 μF) from the OUT pin to ground reduces undershoot magnitude but increase its duration. In the adjustable version, the addition of a capacitor, C_FB, from the OUT pin to the FB pin also improves the transient response.

The TPS736xx-Q1 does not have active pulldown when the output is overvoltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor C_OUT and the internal and external load resistance. The rate of decay is given by Equation 1 or Equation 2, determined by the version.

Equation 1.

Equation 2.

7.3.3 Reverse Current

The NMOS pass element of the TPS736xx-Q1 provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate.

After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. The reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There is additional current flowing into the OUT pin due to the 80-kΩ internal resistor divider to ground (see Figure 29 and Figure 30).

For the TPS73601, reverse current may flow when V_FB is more than 1 V above V_IN.

7.3.4 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS736xx-Q1 has been designed to protect against overload conditions. It was not intended to replace proper heat sinking. Continuously running the TPS736xx-Q1 into thermal shutdown degrades device reliability.

7.4.1 Enable Pin and Shutdown

The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A V_EN below 0.5 V (maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated V_OUT (see Figure 21).

When shutdown capability is not required, EN can be connected to V_IN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after V_IN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power-up. In addition, for V_IN ramp times slower than a few milliseconds, the output may overshoot upon power-up.

Current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section for more information.

7.4.2 Dropout Voltage

The TPS736xx-Q1 uses an NMOS pass transistor to achieve extremely low dropout. When (V_IN – V_OUT) is less than the dropout voltage (V_DO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the R_DS(ON) of the NMOS pass element.

For large step changes in load current, the TPS736xx-Q1 requires a larger voltage drop from V_IN to V_OUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the DC dropout. Values of V_IN – V_OUT above this line ensure normal transient response.

Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (V_IN to V_OUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (V_IN – V_OUT) close to DC dropout levels], the TPS736xx-Q1 can take a couple of hundred microseconds to return to the specified regulation accuracy.