JAJS410P December   2005  – February 2025 TPS74201

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Shutdown
      2. 6.3.2 Power-Good (VQFN Packages Only)
      3. 6.3.3 Internal Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
      5. 7.1.5 Programmable Soft-Start
      6. 7.1.6 Sequencing Requirements
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Protection
        2. 7.4.1.2 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
      2. 8.2.2 Device Nomenclature
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2 Detailed Design Procedure

This is assuming the table for the standard capacitor values is put back in as Table 6-1.

Using Table 7-2, R1 is selected to be 4.12 kΩ for VOUT = 1.5 V and R2 is 4.75 kΩ. Using Table 6-1, CSS is 1000 pF for a 1-ms typical start-up time. For optimal performance, 5-V rail for a Bias supply is used. And R3 of 100 kΩ is selected as the PG bus is used by other devices with additional 100-kΩ pullup resistors.

A CIN of 10 µF is used for better transient performance on the input supply, a CBIAS of 1 µF is used to verify that the Bias supply is solid, and a COUT of 1 µF is used to provide some local capacitance on the output.