JAJSQV0E September   2010  – September 2024 TPS74801-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50 mA
    7. 5.7 Typical Characteristics: IOUT = 1 A
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Programmable Soft-Start
      2. 6.3.2 Sequencing Requirements
      3. 6.3.3 Output Noise
      4. 6.3.4 Enable and Shutdown
      5. 6.3.5 Power Good
      6. 6.3.6 Internal Current Limit
      7. 6.3.7 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input, Output, and Bias Capacitor Requirements
        2. 7.2.2.2 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layout Recommendations and Power Dissipation
        2. 7.4.1.2 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

TPS74801-Q1 DRC Package,10-Pin VSON With Exposed Thermal Pad(Top View)Figure 4-1 DRC Package,10-Pin VSON With Exposed Thermal Pad(Top View)
TPS74801-Q1 RGW Package,20-Pin VQFN With Exposed Thermal Pad(Top View)Figure 4-2 RGW Package,20-Pin VQFN With Exposed Thermal Pad(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DRC (VSON) RGW (VQFN)
BIAS 4 10 I Bias input voltage for error amplifier, reference, and internal control circuits.
EN 5 11 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected.
FB 8 16 I Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
GND 6 12 — Ground
IN 1, 2 5-8 I Input to the device.
NC N/A 2-4, 13, 14, 17 — No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
OUT 9, 10 1, 18-20 O Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to provide stability.
PG 3 9 O Power-good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. Connect a pullup resistor from 10 kΩ to 1 MΩ from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary.
SS 7 15 — Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs.
Thermal Pad — Solder the thermal pad to the ground plane for increased thermal performance.