JAJSN90A december   2022  – may 2023 TPS748A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: IOUT = 50 mA
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Power-Good Output (PG)
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Output Noise
      4. 8.1.4 Estimating Junction Temperature
      5. 8.1.5 Soft Start, Sequencing, and Inrush Current
      6. 8.1.6 Power-Good Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CSS = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V (4), and TJ = –40°C to 150°C, (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 6.0 V
VBIAS BIAS pin voltage range 2.7 6.0 V
VREF Internal reference (Adj.) TA = +25°C 0.796 0.8 0.804 V
VBIAS(UVLO) Rising bias supply UVLO 1.0 1.25 1.75 V
VBIAS(UVLO), HYST Bias supply UVLO hysteresis 20 43 65 mV
ΔVOUT(ΔVIN) Output voltage range VIN = 5 V, IOUT = 1.5 A VREF 3.6 V
Accuracy (1)(5) 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A –1.25 ±0.5 1.25 %
ΔVOUT(ΔIOUT) Line regulation VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V 0.03 %/V
VOUT Load regulation 50 mA ≤ IOUT ≤ 1.5 A 0.09 %/A
VDO(IN) VIN dropout voltage(2) IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V(3) 75 150 mV
VDO(BIAS) VBIAS dropout voltage(2) IOUT = 1.5 A, VIN = VBIAS 1.14 1.35 V
ICL Output current limit VOUT = 80% × VOUT(nom) 2.3 3.1 A
IBIAS BIAS pin current IOUT = 50 mA 0.67 1.1 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V, VIN = 1.1 V, VOUT = 0.8 V 0.9 15 µA
IFB Feedback pin current –0.22 ±0.12 0.22 µA
PSRR Power-supply rejection (VIN to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V 69 dB
300 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V 30 dB
Power-supply rejection (VBIAS to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V 59 dB
300 kHz, IOUT = 1.5 A, VIN = 1.1 V, VOUT = 0.8 V 33 dB
Vn Output noise voltage BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF 7 μVrms x Vout
tSTR Minimum startup time RLOAD for IOUT = 1.0 A, CSS = open 170 µs
ISS Soft-start charging current VSS = 0.4 V 7.5 µA
tSS Soft-start time Css = 10 nF 1.2 ms
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 55 mV
VEN(dg) Enable pin deglitch time 17 µs
IEN Enable pin current VEN = 5 V 0.1 0.3 µA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 2.5 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.125 V
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT 0.01 0.1 µA
TJ Operating junction temperature –40 125 ℃
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 ℃
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 12.
(4) VBIAS = VDO_MAX(BIAS) + VOUT for VOUT ≥ 3.4 V
(5) The device is not tested under conditions where VIN > VOUT + 1.65 V and IOUT = 1.5 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.