JAJSQT2E August   1999  – March 2024 TPS766

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (Legacy Chip)
    5. 5.5 Thermal Information (New Chip)
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Characteristics: Supported ESR Range
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Power-Good Function
      6. 6.3.6 Output Pulldown
      7. 6.3.7 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Adjustable Device Feedback Resistors
        2. 7.2.2.2 Recommended Capacitor Types
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

7.2.2.3 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5Ω. Use a higher value capacitor if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source.

As with most low-dropout regulators, the TPS766 requires an output capacitor connected between OUT and GND to stabilize the internal control loop.

Legacy chip: The minimum recommended capacitance value is 4.7µF and the equivalent series resistance (ESR) is between 300mΩ and 20Ω. Capacitor values of 4.7µF or larger are acceptable, provided the ESR is less than 20Ω. Solid tantalum electrolytic and aluminum electrolytic capacitors are all suitable, provided these capacitors meet the requirements described previously. Ceramic capacitors, with series resistors sized to meet the previously described requirements, are another option.

New chip: The device is designed to be stable using low ESR ceramic capacitors at the input and output. The minimum recommended capacitance value is 2.2μF and the ESR range is up to 2Ω. The supported ESR range depends on the output capacitance, operating junction temperature, and load current conditions. The Typical Characteristics: Supported ESR Range describes the supported ESR range in regards to the output capacitance across temperature for the supported load current range.

Dynamic performance of the device is improved by using an output capacitor. Use an output capacitor within the range specified in the Section 5.3 table for stability.