JAJSTQ9E December   2001  – July 2024 TPS769-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Dissipation Ratings (Legacy Chip)
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
    8. 5.8 Typical Characteristics: Supported ESR Range
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Adjustable Device Feedback Resistors
        2. 7.2.2.2 Recommended Capacitor Types
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
        3. 8.1.1.3 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DBV|5
サーマルパッド・メカニカル・データ
発注情報

5.6 Electrical Characteristics

specified at TJ = –40°C to 125°C, VIN = VOUT(nom) + 1.0V or VIN = 2.5V (whichever is greater), IOUT = 10µA, EN = 0V, CIN = 1.0µF, COUT = 2.2µF (unless otherwise noted); typical values are at TJ = 25ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output voltage Adjustable, legacy chip 1.2V ≤ VOUT ≤ 5.5V, 10µA ≤ IOUT ≤ 100mA, TJ = 25°C VOUT V
1.2V ≤ VOUT ≤ 5.5V, 10µA ≤ IOUT ≤ 100mA 0.97 × VOUT 1.03 × VOUT
Fixed, legacy chip 10µA ≤ IOUT ≤ 100mA, TJ = 25°C, VOUT(nom) + 1V < VIN < 10V VOUT
10µA ≤ IOUT ≤ 100mA, VOUT(nom) + 1V < VIN < 10V 0.97 × VOUT 1.03 × VOUT
New chip 10µA ≤ IOUT ≤ 100mA, VOUT(nom) + 1V < VIN < 16V 0.988 × VOUT 1.012 × VOUT
VFB Feedback voltage Legacy chip 1.224 V
New chip 1.2
IQ Quiescent current (GND current) Legacy chip EN = 0V, 0mA ≤ IOUT ≤ 100mA, TJ = +25°C 17 µA
EN = 0V, IOUT = 100mA 28
New chip EN = 0V, IOUT = 0mA (adjustable) 50 80
EN = 0V, IOUT = 0mA (fixed) 55 95
EN = 0V, IOUT = 100mA 620
ΔVOUT(ΔVOUT) Output voltage line regulation (ΔVOUT/VOUT) Legacy chip VOUT(NOM) +1.0V ≤ VIN ≤ 10V, IOUT = 100mA, TJ = 25℃ 0.04 %/V
0.032
New chip VOUT(NOM) +1.0V ≤ VIN ≤ 16V, IOUT = 10µA 0.032
ΔVOUT(ΔIOUT) Output voltage load regulation Legacy chip 0mA ≤ IOUT ≤ 100mA, TJ = 25°C 12 mV
New chip 20
Vn Output noise voltage Legacy chip BW = 300Hz to 50kHz, COUT = 10µF, TJ = 25℃ 190 µVRMS
New chip BW = 300Hz to 50kHz, IOUT = 100mA,  COUT = 4.7µF 165
BW = 10Hz to 100kHz, IOUT = 100mA,  COUT = 4.7µF 195
TSD(shutdown) Thermal shutdown temperature New chip Temperature increasing 173 ºC
TSD(reset) Thermal shutdown reset temperature New chip Temperature falling 157 ºC
ICL Output current limit Legacy chip VOUT = 0V 350 750 mA
New chip 370 450
ISTANDBY Standby current Legacy chip EN = VIN , 2.7V < VIN < 10V 1 µA
EN = VIN , 2.7V < VIN < 10V 2
New chip EN = VIN , 2.5V < VIN < 16V 0.9
EN = VIN , 2.5V < VIN < 16V 2.75
IFB Feedback pin current Legacy chip VFB = 1.224V –1 1 µA
Newchip VFB = 1.2V –0.1 0.1
EN High level enable input voltage Legacy chip 2.7V ≤ VIN ≤ 10V 1.7 V
Low level enable input voltage 0.9
High level enable input voltage New chip 2.5V ≤ VIN ≤ 16V 1.6
Low level enable input voltage 0.415
PSRR Power-supply ripple rejection Legacy chip IOUT = 100mA, f = 1kHz, COUT = 10µF, TJ = 25 ℃ 60 dB
New chip IOUT = 100mA, f = 1kHz, COUT = 4.7µF, TJ = 25℃ 58
IEN Input current (EN) Legacy chip EN = 0V –1 0 1 µA
EN = VIN –1 1
New chip EN = 0V –0.75 –0.4 0.02
EN = 6V –0.01 0.01
VDO Dropout voltage TPS76928-Q1 (legacy chip) IOUT = 50mA 60 mV
IOUT = 50mA, TJ = –40℃ to 125℃ 125
IOUT = 100mA 122
IOUT = 100mA, TJ = –40℃ to 125℃ 245
TPS76928-Q1 (new chip) IOUT = 50mA 120
IOUT = 50mA, TJ = –40℃ to 125℃ 184
IOUT = 100mA 150
IOUT = 100mA, TJ = –40℃ to 125℃ 218
TPS76930-Q1 (legacy chip) IOUT = 50mA 57
IOUT = 50mA, TJ = –40℃ to 125℃ 115
IOUT = 100mA 115
IOUT = 100mA, TJ = –40℃ to 125℃ 230
TPS76930-Q1 (new chip) IOUT = 50mA 120
IOUT = 50mA, TJ = –40℃ to 125℃ 184
IOUT = 100mA 150
IOUT = 100mA, TJ = –40℃ to 125℃ 218
TPS76933-Q1 (legacy chip) IOUT = 50mA 48
IOUT = 50mA, TJ = –40℃ to 125℃ 100
IOUT = 100mA 98
IOUT = 100mA, TJ = –40℃ to 125℃ 200
TPS76933-Q1 (new chip) IOUT = 50mA 120
IOUT = 50mA, TJ = –40℃ to 125℃ 184
IOUT = 100mA 150
IOUT = 100mA, TJ = –40℃ to 125℃ 218
TPS76950-Q1 (legacy chip) IOUT = 50mA 35
IOUT = 50mA, TJ = –40℃ to 125℃ 85
IOUT = 100mA 71
IOUT = 100mA, TJ = –40℃ to 125℃ 170
TPS76950-Q1 (new chip) IOUT = 50mA 120
IOUT = 50mA, TJ = –40℃ to 125℃ 184
IOUT = 100mA 150
IOUT = 100mA, TJ = –40℃ to 125℃ 218
VUVLO+ Rising bias supply UVLO TPS769-Q1 (new chip) VIN rising, –40℃ ≤ TJ ≤ 125℃ 2.2 2.4 V
VUVLO– Falling bias supply UVLO VIN falling, –40℃ ≤ TJ ≤ 125℃ 1.9 2.07
VUVLO(HYST) UVLO hysteresis –40℃ ≤ TJ ≤ 125℃ 0.130