SBVS083E January 2007 – January 2015 TPS780
PRODUCTION DATA.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS780 family of LDOs is factory-programmable to have a fixed output. Note that during start-up or steady-state conditions, do not allow the EN pin voltage to exceed VIN + 0.3 V.
8.2 Typical Application
Figure 56. Typical Application Circuit
8.2.1 Design Requirements
Table 3. Design Paramters
| PARAMETER | DESIGN REQUIREMENT |
|---|---|
| Input Voltage | 5 V |
| Output Voltage High | 3.6 V |
| Output Voltage Low | 2 V |
| Maximum Output Current | 100 mA |
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the GND pin current, and power the load. Select input and output capacitors based on application needs.
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located near the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.
The TPS780 family is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1.0 Ω. With tolerance and dc bias effects, the minimum capacitance to ensure stability is 1 μF.
8.2.2.2 Dropout Voltage
The TPS780 family uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is the linear region of operation and the input-to-output resistance is the RDS(on) of the PMOS pass element. VDO approximately scales with output current because the PMOS device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Typical Characteristics. Refer to application report SLVA207, Understanding LDO Dropout, available from www.ti.com.
8.2.2.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response. For more information, see Figure 48.
8.2.2.4 Minimum Load
The TPS780 family is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS780 employs an innovative, low-current circuit under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. See for the load transient response.
8.2.3 Application Curves
| CIN = 1 μF, COUT = 2.2 μF, VVSET = 1.2 V, VIN = 2.7 V |
| VIN = 2.7 V, VOUT = 1.2 V, COUT = 2.2 μF |
8.3 Do's and Don'ts
Place at least one 1-μF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND of the regulator.
Do not exceed the absolute maximum ratings.