For best performance, connect a low-output impedance power supply directly to the IN pin of the TPS780. Inductive impedances between the input supply and the IN pin create significant voltage excursions at the IN pin during start-up or load transient events. If inductive impedances are unavoidable, use an input capacitor.

9.1 Powering the MSP430 Microcontroller

Several versions of the TPS780 are ideal for powering the MSP430 microcontroller. Table 4 shows potential applications of some voltage versions.

The TPS780 family offers many output voltage versions to allow designers to optimize the supply voltage for the processing speed required of the MSP430. This flexible architecture minimizes the supply current consumed by the particular MSP430 application. The MSP430 total system power can be reduced by substituting the 500-nA I_Q TPS780 series LDO in place of an existing ultralow I_Q LDO (typical best case = 1 μA). Additionally, DVS allows for increasing the clock speed in active mode (MSP430 V_CC = 3.6 V). The 3.6-V V_CC reduces the MSP430 time in active mode. In low-power mode, MSP430 system power can be further reduced by lowering the MSP430 V_CC to 2.2 V in sleep mode.

Key features of the TPS780 series are an ultralow quiescent current (500 nA), DVS, and miniaturized packaging. The TPS780 family are available in SON-6 and TSOT-23 packages. Figure 59 shows a typical MSP430 circuit powered by an LDO without DVS. Figure 60 is an MSP430 circuit using a TPS780 LDO that incorporates an integrated DVS, thus simplifying the circuit design. In a circuit without DVS, as Figure 59 illustrates, V_CC is always at 3.0 V. When the MSP430 goes into sleep mode, V_CC remains at 3.0 V; if DVS is applied, V_CC could be reduced in sleep mode. In Figure 60, the TPS780 LDO with integrated DVS maintains 3.6-V V_CC until a logic high signal from the MSP430 forces V_OUT to level shift V_OUT from 3.6 V down to 2.2 V, thus reducing power in sleep mode.

Figure 59. Typical LDO Without DVS

Figure 60. TPS780 With Integrated DVS

The other benefit of DVS is that it allows a higher V_CC voltage on the MSP430, increasing the clock speed and reducing the active mode dwell time.

The total system power savings is outlined in Table 5, Table 6, and Table 7. In Table 5, the MSP430 power savings are calculated for various MSP430 devices using a TPS780 series with integrated DVS versus a standard ultralow IQ LDO without DVS. In Table 6, the TPS780 series quiescent power is calculated for a VIN of 4.2 V, with the same VIN used for the ultralow IQ LDO. Quiescent power dissipation in an LDO is the VIN voltage times the ground current, because zero load is applied. After the dissipation power is calculated for the individual LDOs in Table 6, simple subtraction outputs the LDO power savings using the TPS780 series. Table 7 calculates the total system power savings using a TPS780 series LDO in place of an ultralow IQ 1.2-μA LDO in an MSP430F1121 application. There are many different versions of the MSP430. Actual power savings vary depending on the selected device.