JAJS343L January   2005  – February 2022 TPS799

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Start Up
      4. 7.3.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Output Noise
        3. 8.2.2.3 Dropout Voltage
        4. 8.2.2.4 Transient Response
        5. 8.2.2.5 Minimum Load
        6. 8.2.2.6 Feedback Capacitor Requirements (TPS79901 Only)
      3. 8.2.3 Application Curve
    3. 8.3 What To Do and What Not To Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Thermal Information
        1. 10.1.2.1 Thermal Protection
        2. 10.1.2.2 Power Dissipation
        3. 10.1.2.3 Package Mounting
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-BB55BF56-7A7C-43E4-8F68-A7DED80AA950-low.gifFigure 5-1 DDC Package (Fixed),5-Pin SOT-23-THIN(Top View)
GUID-3EC74022-9B07-4331-AB35-4B2AF8C74D4D-low.gifFigure 5-3 YZU Package (Fixed),5-Pin DSBGA(Top View)
GUID-3F6CAEE1-9D7F-4A80-86FA-72AFB862C58E-low.gifFigure 5-5 DRV Package (Fixed),6-Pin WSON With Exposed Thermal Pad(Top View)
GUID-B1240B6F-6446-4B8E-B7BC-2410B048EAF4-low.gifFigure 5-2 DDC Package (Adjustable),5-Pin SOT-23-THIN(Top View)
GUID-EBC165B4-47A2-43C2-B466-FB81456F8E9C-low.gifFigure 5-4 YZU Package (Adjustable),5-Pin DSBGA (Top View)
GUID-24CFFAC7-20A7-429D-90AD-BCD1899CD6DB-low.gifFigure 5-6 DRV Package (Adjustable),6-Pin WSON With Exposed Thermal Pad (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME DDC YZU DRV
IN 1 C3 6 I Input supply.
GND 2 B2 3, Pad — Ground. The pad must be tied to GND.
EN 3 A1 4 I Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used.
NR 4 A3 2 — Fixed voltage versions only. Noise reduction; connecting this pin to an external capacitor bypasses noise generated by the internal band gap. This capacitor allows output noise to be reduced to very low levels.
FB 4 A3 2 I Adjustable voltage version only. Feedback; this pin is the input to the control loop error amplifier, and sets the output voltage of the device.
OUT 5 C1 1 O Output of the regulator. To assure stability, a small ceramic capacitor (total typical capacitance ≥ 2 μF) is required from this pin to ground.
N/C — — 5 — Not internally connected. This pin must either be left open, or tied to GND.