JAJSO94B june   2022  – august 2023 TPS7A15

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excellent Transient Response
      2. 7.3.2 Active Overshoot Pulldown Circuitry
      3. 7.3.3 Global Undervoltage Lockout (UVLO)
      4. 7.3.4 Enable Input
      5. 7.3.5 Internal Foldback Current Limit
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
      2. 8.1.2  Input, Output, and Bias Capacitor Requirements
      3. 8.1.3  Dropout Voltage
      4. 8.1.4  Behavior During Transition From Dropout Into Regulation
      5. 8.1.5  Device Enable Sequencing Requirement
      6. 8.1.6  Load Transient Response
      7. 8.1.7  Undervoltage Lockout Circuit Operation
      8. 8.1.8  Power Dissipation (PD)
      9. 8.1.9  Estimating Junction Temperature
      10. 8.1.10 Recommended Area for Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

This design example is powered by a rechargeable battery that can be a building block in many portable applications. Noise-sensitive portable electronics require an efficient, small-size solution for the power supply. Traditional LDOs are known for low efficiency in contrast to low-input, low-output voltage (LILO) LDOs, such as the TPS7A15. Using a bias rail in the TPS7A15 allows the device to operate at a lower input voltage, thus reducing the voltage drop across the pass transistor and maximizing device efficiency. The low voltage drop allows the efficiency of the LDO to approximate that of a DC/DC converter. Equation 8 calculates the efficiency for this design.

Equation 8. Efficiency = η = POUT / PIN × 100 % = (VOUT × IOUT) / (VIN × IIN + VBIAS × IBIAS) × 100 %

Equation 8 reduces to Equation 9 because the design example load current is much greater than the quiescent current of the bias rail.

Equation 9. Efficiency = η = (VOUT × IOUT) / (VIN × IIN) × 100%

For this design example, the 0.9-V output version (TPS7A1509) is selected. A nominal 1.05-V input supply comes from a DC/DC converter connected to the battery. Use a minimum 1.0-μF input capacitor to minimize the effect of resistance and inductance between the 1.05-V source and the LDO input. Use a minimum 2.2-μF output capacitor for stability and good load transient response.

The dropout voltage (VDO) is less than 80 mV maximum at a 0.9-V output voltage and 400-mA output current, so there are no dropout issues with a minimum input voltage of 1.0 V and a maximum output current of 200 mA. In addition, the TPS7A15 is designed to meet key specifications so long as the input voltage is at least 100 mV greater than the output voltage.