JAJSGX3A
February 2019 – March 2019
TPS7A16A-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
代表的なアプリケーションの回路図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Enable (EN)
7.3.2
Regulated Output (VOUT)
7.3.3
PG Delay Timer (DELAY)
7.4
Device Functional Modes
7.4.1
Power-Good
7.4.1.1
Power-Good Delay and Delay Capacitor
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
TPS7A16A-Q1 Circuit as an Adjustable Regulator
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Adjustable Voltage Operation
8.2.1.2.1.1
Resistor Selection
8.2.1.2.2
Capacitor Recommendations
8.2.1.2.3
Input and Output Capacitor Requirements
8.2.1.2.4
Feed-Forward Capacitor (Only for Adjustable Version)
8.2.1.2.5
Transient Response
8.2.1.3
Application Curves
8.2.2
Automotive Applications
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Device Recommendations
8.2.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Additional Layout Considerations
10.1.2
Power Dissipation
10.1.3
Thermal Considerations
10.2
Layout Examples
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントの更新通知を受け取る方法
11.2
コミュニティ・リソース
11.3
商標
11.4
静電気放電に関する注意事項
11.5
Glossary
12
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DGN|8
MPDS046F
サーマルパッド・メカニカル・データ
DGN|8
PPTD229A
発注情報
jajsgx3a_oa
jajsgx3a_pm
10.2
Layout Examples
Figure 19.
Schematic for Suggested Layout
Figure 20.
Suggested Layout: Top Layer
Figure 21.
Suggested Layout: Bottom Layer