JAJSN43A December   2021  – September 2022 TPS7A21

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Enable (EN)
      2. 7.3.2 Low Output Noise
      3. 7.3.3 Active Discharge
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Foldback Current Limit
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Overload Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Load Transient Response
      4. 8.1.4 Undervoltage Lockout (UVLO) Operation
      5. 8.1.5 Power Dissipation (PD)
      6. 8.1.6 Estimating Junction Temperature
      7. 8.1.7 Recommended Area For Continuous Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 DSBGA Mounting
        2. 8.4.1.2 DSBGA Light Sensitivity
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • YWD|4
サーマルパッド・メカニカル・データ
発注情報

Foldback Current Limit

The TPS7A21 has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a brick-wall scheme to a foldback scheme at the foldback voltage (VFOLDBACK).

In a high-load current fault with the output voltage above VFOLDBACK, the brick-wall scheme limits the output current to the current limit (ICL). When the output voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current when the output voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-circuit current limit (ISC). ICL and ISC are listed in the Section 6.5 table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the regulator begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the output is shorted and the output voltage is less than VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition persists, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note.

Figure 7-1 shows a diagram of the foldback current limit.

GUID-25903D0F-4DCB-4B40-A374-B4E893BAA9CA-low.gifFigure 7-1 Foldback Current Limit