JAJSGN3C December   2018  – December 2022 TPS7A25

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable
      2. 8.3.2 Dropout Voltage
      3. 8.3.3 Current Limit
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 Power Good
      7. 8.3.7 Active Overshoot Pulldown Circuitry
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Functional Mode Comparison
      2. 8.4.2 Normal Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Disabled
        1.       Application and Implementation
          1. 9.1 Application Information
            1. 9.1.1 Adjustable Device Feedback Resistors
            2. 9.1.2 Recommended Capacitor Types
            3. 9.1.3 Input and Output Capacitor Requirements
            4. 9.1.4 Reverse Current
            5. 9.1.5 Feed-Forward Capacitor (CFF)
            6. 9.1.6 Power Dissipation (PD)
            7. 9.1.7 Estimating Junction Temperature
            8. 9.1.8 Special Consideration for Line Transients
          2. 9.2 Typical Application
            1. 9.2.1 Design Requirements
            2. 9.2.2 Detailed Design Procedure
              1. 9.2.2.1 Transient Response
              2. 9.2.2.2 Selecting Feedback Divider Resistors
              3. 9.2.2.3 Thermal Dissipation
            3. 9.2.3 Application Curve
          3. 9.3 Power Supply Recommendations
          4. 9.4 Layout
            1. 9.4.1 Layout Guidelines
            2. 9.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRV|6
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note.

Figure 8-3 depicts a diagram of the current limit.

GUID-7302E671-69BC-4619-A04B-22C2F6FF4F19-low.gif Figure 8-3 Current Limit